{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:11:08Z","timestamp":1729660268777,"version":"3.28.0"},"reference-count":27,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/sccc.2003.1245446","type":"proceedings-article","created":{"date-parts":[[2004,6,22]],"date-time":"2004-06-22T20:27:43Z","timestamp":1087936063000},"page":"60-69","source":"Crossref","is-referenced-by-count":1,"title":["Efficient computation of algebraic operations over dynamically reconfigurable systems specified by rewriting-logic environments"],"prefix":"10.1109","author":[{"given":"M.","family":"Ayala-Rincon","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.B.","family":"Nogueira","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C.","family":"Llanos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.P.","family":"Jacobi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.W.","family":"Hartenstein","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"article-title":"Introduction to Algorithms","year":"2001","author":"cormen","key":"ref10"},{"key":"ref11","first-page":"174","article-title":"Lava: Hardware Design in Haskell","author":"claessen","year":"1998","journal-title":"Proc ICFP"},{"key":"ref12","first-page":"289","author":"diaconescu","year":"0","journal-title":"Logical foundations of CafeOBJ"},{"key":"ref13","article-title":"A Scalable, Parallel and Reconfigurable Datapath Architecture","author":"hartenstein","year":"1995","journal-title":"6th Int Symp IC Technology System and Applications ISIC-95"},{"key":"ref14","article-title":"Theorem Proving Support for Hardware Verification, invited talk","author":"kapur","year":"2000","journal-title":"International Workshop on First-Order Theorem Proving"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/PL00010808"},{"key":"ref16","first-page":"103","article-title":"Mechanizing Verification of Arithmetic Circuits: SRT Division","volume":"1346","author":"kapur","year":"1997","journal-title":"Proc 7th FSTTCS"},{"key":"ref17","first-page":"263","article-title":"Computational Problems in Abstract Algebra","author":"knuth","year":"1970","journal-title":"Simple Word Problems in Universal Algebras"},{"key":"ref18","first-page":"256","article-title":"Systolic Arrays for VLSI","author":"kung","year":"1979","journal-title":"Sparse Matrix Proc 1978"},{"journal-title":"VLSI Array Processors","year":"1987","author":"kung","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.2003.1232830"},{"key":"ref27","first-page":"595","article-title":"Hardware Synthesis from Term Rewriting Systems","author":"hoe","year":"1999","journal-title":"Proc of the 10th IFIP Int Conf on VLSI &#x2013; VLSI'99"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/S1571-0661(04)80601-7"},{"journal-title":"Computer Algorithms Introduction to Design and Analysis","year":"1999","author":"baase","key":"ref6"},{"key":"ref5","doi-asserted-by":"crossref","DOI":"10.1017\/CBO9781139172752","author":"baader","year":"1998","journal-title":"Term Rewriting and All That"},{"key":"ref8","first-page":"187","author":"clavel","year":"0","journal-title":"Maude Specification and programming in rewriting logic"},{"key":"ref7","first-page":"155","author":"borovansk\u00fd","year":"0","journal-title":"ELAN from a rewriting logic point of view"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/40.768501"},{"key":"ref9","first-page":"95","article-title":"Combining Higher-Order and First-Order Computation Using rho-Calculus: Towards a Semantics of ELAN","volume":"7","author":"cirstea","year":"2000","journal-title":"Frontiers of Combining Systems 2 Studies in Logic and Computation"},{"journal-title":"Parallel Computation Models and Methods","year":"1997","author":"akl","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/S0304-3975(01)00356-5"},{"journal-title":"Coarse-grained Reconfigurable Architectures Design Space Exploration","year":"2001","author":"nageldinger","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/10721975_1"},{"key":"ref24","article-title":"Design and Venfication of Speculative Processors","author":"shen","year":"1998","journal-title":"Technical Report 400"},{"key":"ref23","article-title":"Kress Array Explorer: A New CAD Environment to Optimize Reconfigurable Datapath Array Architectures","author":"hartenstein","year":"2000","journal-title":"5th Asia and South Pacific Design Automation Conference &#x2013; ASP-DAC 2000"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305187"},{"key":"ref25","article-title":"Modeling and Venfication of ISA Implementations","author":"shen","year":"1998","journal-title":"Technical Report 400"}],"event":{"name":"23rd International Conference of the Chilean Computer Science Society, 2003. SCCC 2003.","location":"Chillan, Chile"},"container-title":["23rd International Conference of the Chilean Computer Science Society, 2003. SCCC 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8814\/27899\/01245446.pdf?arnumber=1245446","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T08:16:38Z","timestamp":1497600998000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1245446\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/sccc.2003.1245446","relation":{},"subject":[]}}