{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T18:47:59Z","timestamp":1760122079668},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,6]]},"DOI":"10.1109\/sies.2011.5953649","type":"proceedings-article","created":{"date-parts":[[2011,7,20]],"date-time":"2011-07-20T16:50:22Z","timestamp":1311180622000},"page":"1-8","source":"Crossref","is-referenced-by-count":6,"title":["HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs"],"prefix":"10.1109","author":[{"given":"Jaume","family":"Joven","sequence":"first","affiliation":[]},{"given":"Per","family":"Strict","sequence":"additional","affiliation":[]},{"given":"David","family":"Castells-Rufas","sequence":"additional","affiliation":[]},{"given":"Akash","family":"Bagdia","sequence":"additional","affiliation":[]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[]},{"given":"Jordi","family":"Carrabina","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Nios II Embedded Processor - Altera","year":"0","key":"ref10"},{"journal-title":"Altera Floating Point Megafunctions","year":"0","key":"ref11"},{"journal-title":"Virtex-5 APU Floating-Point Unit V1 01a","year":"0","key":"ref12"},{"journal-title":"Floating-Point Operator v5 0","year":"0","key":"ref13"},{"journal-title":"Aeroflex Gaisler","year":"0","key":"ref14"},{"journal-title":"Create TIE Processor Extensions","year":"2006","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878305"},{"journal-title":"ARM AMBA 2 0 ARB-APB Overview","year":"2005","key":"ref17"},{"journal-title":"ARM Cortex-R4(F) – ARM Processor","year":"2006","key":"ref18"},{"journal-title":"Xilinx microblaze soft processor core","year":"0","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"ref3","first-page":"681","article-title":"The future of multiprocessor systems-on-chips","author":"wolf","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"journal-title":"Multi-layer AHB Technical Overview","year":"2001","key":"ref6"},{"journal-title":"Networks on Chips Technology and Tools","year":"2006","author":"benini","key":"ref5"},{"journal-title":"ARM Cortex-M1 – ARM Processor","year":"2007","key":"ref8"},{"journal-title":"AMBA 3 AXI overview","year":"2005","key":"ref7"},{"journal-title":"Multiprocessor Systems-on-Chips","year":"2005","author":"jerraya","key":"ref2"},{"journal-title":"IEEE 754 Standard for Binary Floating-Point Arithmetic","year":"1985","key":"ref1"},{"journal-title":"ARM Cortex-M3 – ARM Processor","year":"2004","key":"ref9"}],"event":{"name":"2011 6th IEEE International Symposium on Industrial Embedded Systems (SIES)","start":{"date-parts":[[2011,6,15]]},"location":"Vasteras","end":{"date-parts":[[2011,6,17]]}},"container-title":["2011 6th IEEE International Symposium on Industrial and Embedded Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5937480\/5953643\/05953649.pdf?arnumber=5953649","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,2,5]],"date-time":"2020-02-05T15:51:36Z","timestamp":1580917896000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5953649\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/sies.2011.5953649","relation":{},"subject":[],"published":{"date-parts":[[2011,6]]}}}