{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T13:51:18Z","timestamp":1730296278897,"version":"3.28.0"},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,6]]},"DOI":"10.1109\/sies.2011.5953688","type":"proceedings-article","created":{"date-parts":[[2011,7,20]],"date-time":"2011-07-20T16:50:22Z","timestamp":1311180622000},"page":"91-94","source":"Crossref","is-referenced-by-count":5,"title":["Large drilling machine control code &amp;#x2014; Parallelisation and WCET speedup"],"prefix":"10.1109","author":[{"given":"Mike","family":"Gerdes","sequence":"first","affiliation":[]},{"given":"Julian","family":"Wolf","sequence":"additional","affiliation":[]},{"given":"Irakli","family":"Guliashvili","sequence":"additional","affiliation":[]},{"given":"Theo","family":"Ungerer","sequence":"additional","affiliation":[]},{"given":"Michael","family":"Houston","sequence":"additional","affiliation":[]},{"given":"Guillem","family":"Bernat","sequence":"additional","affiliation":[]},{"given":"Stefan","family":"Schnitzler","sequence":"additional","affiliation":[]},{"given":"Hans","family":"Regler","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"103","article-title":"Towards WCET Analysis of Multicore Architectures using UPPAAL","author":"gustavsson","year":"0","journal-title":"Proc of WCET 2010"},{"key":"ref3","first-page":"37","article-title":"Migration of Automotive Real-Time Software to Multicore Systems: First Steps towards an Automated Solution","author":"schneider","year":"0","journal-title":"Proc WiP Session of ECRTS 2010"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISORC.2010.31"},{"journal-title":"Rapita-Systems Ltd","article-title":"RapiTime White Paper","year":"2008","key":"ref5"},{"key":"ref8","first-page":"122","article-title":"A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware","volume":"6566","author":"metzlaff","year":"0","journal-title":"Proceedings of ARCS 2011"},{"key":"ref7","first-page":"2","article-title":"How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT","volume":"5974","author":"mische","year":"0","journal-title":"Proc ARC 2010"},{"key":"ref2","first-page":"92","article-title":"WCET Analysis of a Parallel 3D Multigrid Solver Executed on the MERASA Multi-Core","author":"rochange","year":"0","journal-title":"Proc of WCET 2010"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.78"}],"event":{"name":"2011 6th IEEE International Symposium on Industrial Embedded Systems (SIES)","start":{"date-parts":[[2011,6,15]]},"location":"Vasteras, Sweden","end":{"date-parts":[[2011,6,17]]}},"container-title":["2011 6th IEEE International Symposium on Industrial and Embedded Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5937480\/5953643\/05953688.pdf?arnumber=5953688","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T08:22:45Z","timestamp":1490084565000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5953688\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/sies.2011.5953688","relation":{},"subject":[],"published":{"date-parts":[[2011,6]]}}}