{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,3]],"date-time":"2026-03-03T23:36:29Z","timestamp":1772580989994,"version":"3.50.1"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.1109\/sies.2018.8442100","type":"proceedings-article","created":{"date-parts":[[2018,8,23]],"date-time":"2018-08-23T22:10:52Z","timestamp":1535062252000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu"],"prefix":"10.1109","author":[{"given":"Christian","family":"Fibich","sequence":"first","affiliation":[]},{"given":"Stefan","family":"Tauner","sequence":"additional","affiliation":[]},{"given":"Peter","family":"Rossler","sequence":"additional","affiliation":[]},{"given":"Martin","family":"Horauer","sequence":"additional","affiliation":[]},{"given":"Herbert","family":"Taucher","sequence":"additional","affiliation":[]},{"given":"Martin","family":"Matschnig","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2513673"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2014.2320556"},{"key":"ref10","year":"2015"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645550"},{"key":"ref5","year":"2017","journal-title":"Vivado Design Suite User Guide High-Level Synthesis (UG902 (v2012 4))"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TSMC.1979.4310076"},{"key":"ref7","year":"2013","journal-title":"AT01180 Barcode and QR code scanner User Guide"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjjip.17.242"},{"key":"ref9","author":"beer","year":"2015","journal-title":"Quirc"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4020-8588-8","author":"coussy","year":"2008","journal-title":"High-Level Synthesis from Algorithm to Digital Circuit"}],"event":{"name":"2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES)","location":"Graz","start":{"date-parts":[[2018,6,6]]},"end":{"date-parts":[[2018,6,8]]}},"container-title":["2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8410983\/8442074\/08442100.pdf?arnumber=8442100","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,8]],"date-time":"2020-11-08T05:30:20Z","timestamp":1604813420000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8442100\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/sies.2018.8442100","relation":{},"subject":[],"published":{"date-parts":[[2018,6]]}}}