{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T21:48:08Z","timestamp":1725400088195},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,10]]},"DOI":"10.1109\/sips.2007.4387556","type":"proceedings-article","created":{"date-parts":[[2007,11,21]],"date-time":"2007-11-21T11:31:17Z","timestamp":1195644677000},"page":"267-272","source":"Crossref","is-referenced-by-count":1,"title":["Spatial Feature Based Video Scaling Scheme and its FPGA Implementation for Video Standards Conversion"],"prefix":"10.1109","author":[{"given":"Baris","family":"Uyar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Murat","family":"Sayinta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toygar","family":"Akgun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bulent","family":"Orencik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yucel","family":"Altunbasak","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707886"},{"key":"ref3","article-title":"Method and apparatus for enhancing the resolution of a digital image","author":"altunbasak","year":"0","journal-title":"filed at the European Patent Office (EPO) application number 06251100 1 Mar 2006 filed at the US Patent Office (application number pending)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICICIC.2006.226"},{"key":"ref5","article-title":"Real-time fpga-based architecture for bicubic interpolation: An application for digital image scaling","author":"aurelio","year":"2005","journal-title":"International Conference on Reconfigurable Computing and FPGAs (ReCon-Fig'05)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2003.1231927"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/38.988747"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2001.958257"}],"event":{"name":"2007 IEEE Workshop on Signal Processing Systems","start":{"date-parts":[[2007,10,17]]},"location":"Shanghai, China","end":{"date-parts":[[2007,10,19]]}},"container-title":["2007 IEEE Workshop on Signal Processing Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4387497\/4387498\/04387556.pdf?arnumber=4387556","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T11:29:55Z","timestamp":1489663795000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4387556\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,10]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/sips.2007.4387556","relation":{},"ISSN":["1520-6130"],"issn-type":[{"type":"print","value":"1520-6130"}],"subject":[],"published":{"date-parts":[[2007,10]]}}}