{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T11:15:24Z","timestamp":1742382924188},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,10]]},"DOI":"10.1109\/sips.2009.5336268","type":"proceedings-article","created":{"date-parts":[[2009,12,9]],"date-time":"2009-12-09T15:58:30Z","timestamp":1260374310000},"page":"285-290","source":"Crossref","is-referenced-by-count":11,"title":["Massively parallel implementation of cyclic LDPC codes on a general purpose graphics processing unit"],"prefix":"10.1109","author":[{"given":"Hyunwoo","family":"Ji","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junho","family":"Cho","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wonyong","family":"Sung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","article-title":"Edge Stream Oriented LDPC Decoding","author":"falca?o","year":"2008","journal-title":"Parallel Distributed and Network-Based Processing 15th EUROMICRO International Conference"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.2007.4387546"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/18.910578"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/18.959255"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ISIT.2002.1023727"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2004.836563"},{"journal-title":"The IEEE 802 16 Working Group","year":"0","key":"3"},{"journal-title":"The Digital Video Broadcasting Standard","year":"0","key":"2"},{"key":"1","doi-asserted-by":"crossref","DOI":"10.7551\/mitpress\/4347.001.0001","author":"gallager","year":"1963","journal-title":"Low Density Parity Check Codes"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/26.768759"},{"key":"7","first-page":"127","article-title":"A 54 Mbps (3, 6)-regular FPGA LDPC decoder","author":"zhang","year":"2001","journal-title":"Proc IEEE Workshop on Signal Processing Systems (SiPS)"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1981.1056404"},{"key":"5","first-page":"83","article-title":"Massive Parallel LDPC Decoding on GPU","author":"falca?o","year":"2008","journal-title":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2008)"},{"journal-title":"The IEEE 802 11n Working Group","year":"0","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/18.748992"},{"year":"0","key":"8"}],"event":{"name":"2009 IEEE Workshop on Signal Processing Systems (SiPS)","start":{"date-parts":[[2009,10,7]]},"location":"Tampere, Finland","end":{"date-parts":[[2009,10,9]]}},"container-title":["2009 IEEE Workshop on Signal Processing Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5319413\/5336222\/05336268.pdf?arnumber=5336268","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,24]],"date-time":"2019-05-24T07:32:28Z","timestamp":1558683148000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5336268\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,10]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/sips.2009.5336268","relation":{},"subject":[],"published":{"date-parts":[[2009,10]]}}}