{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:48:45Z","timestamp":1759146525974,"version":"3.41.2"},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2011,10,1]],"date-time":"2011-10-01T00:00:00Z","timestamp":1317427200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2011,10,1]],"date-time":"2011-10-01T00:00:00Z","timestamp":1317427200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,10]]},"DOI":"10.1109\/sips.2011.6088975","type":"proceedings-article","created":{"date-parts":[[2011,12,6]],"date-time":"2011-12-06T16:03:50Z","timestamp":1323187430000},"page":"204-209","source":"Crossref","is-referenced-by-count":6,"title":["Generalized interleaving network based on configurable QPP architecture for parallel turbo decoder"],"prefix":"10.1109","author":[{"given":"Shuaijie","family":"Wang","sequence":"first","affiliation":[{"name":"School of Microelectronics, Shanghai Jiao Tong University, 800 Dong Chuan Road, Shanghai, China"}]},{"given":"Jun","family":"Ma","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Shanghai Jiao Tong University, 800 Dong Chuan Road, Shanghai, China"}]},{"given":"Guanghui","family":"He","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Shanghai Jiao Tong University, 800 Dong Chuan Road, Shanghai, China"}]},{"given":"Zhigang","family":"Mao","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Shanghai Jiao Tong University, 800 Dong Chuan Road, Shanghai, China"}]}],"member":"263","reference":[{"key":"3","first-page":"288","article-title":"A 188-size 2.1 mm\/sup 2\/reconfigurable turbo decoder chip with parallel architecture for 3GPP LTE system","author":"cheng-chi","year":"2009","journal-title":"2009 Symp VLSI Circuits"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2005.864450"},{"key":"1","first-page":"1064","article-title":"Near Shannon limit error-correcting coding and decoding: Turbo-codes","volume":"2","author":"berrou","year":"1993","journal-title":"Communications 1993 ICC 93 Geneva Technical Program Conference Record IEEE International Conference on"},{"key":"7","article-title":"Sorting networks and their applications","author":"batcher","year":"1968","journal-title":"Proceedings of the April 30-May 2 1968 Spring Joint Computer Conference Atlantic City New Jersey"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2010.07.001"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280790"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433918"}],"event":{"name":"2011 IEEE Workshop on Signal Processing Systems (SiPS)","start":{"date-parts":[[2011,10,4]]},"location":"Beirut, Lebanon","end":{"date-parts":[[2011,10,7]]}},"container-title":["2011 IEEE Workshop on Signal Processing Systems (SiPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6086638\/6088939\/06088975.pdf?arnumber=6088975","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,17]],"date-time":"2025-07-17T17:55:04Z","timestamp":1752774904000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6088975\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/sips.2011.6088975","relation":{},"subject":[],"published":{"date-parts":[[2011,10]]}}}