{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T21:11:59Z","timestamp":1725657119215},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/sips.2013.6674539","type":"proceedings-article","created":{"date-parts":[[2013,12,4]],"date-time":"2013-12-04T16:22:18Z","timestamp":1386174138000},"page":"395-400","source":"Crossref","is-referenced-by-count":2,"title":["Memory capacity aware non-blocking data transfer on GPGPU"],"prefix":"10.1109","author":[{"given":"Hao-Wei","family":"Liu","sequence":"first","affiliation":[]},{"given":"Hsien-Kai","family":"Kuo","sequence":"additional","affiliation":[]},{"given":"Kuan-Ting","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Bo-Cheng Charles","family":"Lai","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/71.993206"},{"key":"16","first-page":"97","author":"dick","year":"0","journal-title":"Tgff Task graphs for free"},{"key":"13","first-page":"408","author":"satish","year":"0","journal-title":"Optimizing the Use of GPU Memory in Applications with Large Data Sets"},{"journal-title":"Electronic Design Automation Synthesis Verification and Test","year":"2009","author":"wang","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"key":"12","first-page":"1","author":"sundaram","year":"0","journal-title":"A Framework for Efficient and Scalable Execution of Domainspecific Templates on GPUs"},{"journal-title":"Titan Supercomputer","year":"0","key":"3"},{"journal-title":"TEGRA Super Processors","year":"0","key":"2"},{"journal-title":"Tesla Fermi Family Product Overview","year":"0","key":"1"},{"journal-title":"Fermi White Paper","year":"0","key":"10"},{"key":"7","article-title":"Main memory technology direction","author":"kilbuck","year":"2007","journal-title":"Microsoft WinHEC"},{"journal-title":"Processing (APP) SDK","year":"0","key":"6"},{"journal-title":"AMD Accelerated Parallel","year":"0","key":"5"},{"journal-title":"NVidia CUDA","year":"0","key":"4"},{"journal-title":"White Paper WP-05462-001-v01","article-title":"Nvidia quadro dual copy engines","year":"0","key":"9"},{"journal-title":"NVIDIA GeForce GTX 680 Specifications","year":"0","key":"8"}],"event":{"name":"2013 IEEE Workshop on Signal Processing Systems (SiPS)","start":{"date-parts":[[2013,10,16]]},"location":"Taipei City","end":{"date-parts":[[2013,10,18]]}},"container-title":["SiPS 2013 Proceedings"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6670311\/6674470\/06674539.pdf?arnumber=6674539","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T19:49:55Z","timestamp":1490212195000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6674539\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/sips.2013.6674539","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}