{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T06:52:45Z","timestamp":1729666365577,"version":"3.28.0"},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/sips.2017.8109982","type":"proceedings-article","created":{"date-parts":[[2017,11,16]],"date-time":"2017-11-16T21:54:21Z","timestamp":1510869261000},"page":"1-6","source":"Crossref","is-referenced-by-count":4,"title":["Design space exploration of dataflow-based Smith-Waterman FPGA implementations"],"prefix":"10.1109","author":[{"given":"Simone","family":"Casale-Brunet","sequence":"first","affiliation":[]},{"given":"Endri","family":"Bezati","sequence":"additional","affiliation":[]},{"given":"Marco","family":"Mattavelli","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/BICTA.2010.5645235"},{"key":"ref11","article-title":"Applying gpus for smith-waterman sequence alignment acceleration","volume":"1","author":"phong","year":"2014","journal-title":"GSTF International Journal on Computing (JoC)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/icbbe.2011.5780005"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/5.381846"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-6345-1_3"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-6184-6_12"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.image.2013.08.008"},{"journal-title":"Information Technology - MPEG Systems Technologies - Part 4 Codec Configuration Representation","year":"2011","key":"ref17"},{"key":"ref18","article-title":"CAL language report: Specification of the CAL Actor Language","author":"eker","year":"2003","journal-title":"Electronics Research Laboratory University of California at Berkeley Tech Rep UCB\/ERL M03\/48"},{"journal-title":"Analysis and optimization of dynamic dataflow programs","year":"2015","author":"simone","key":"ref19"},{"journal-title":"TURNUS","year":"0","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1982.1653825"},{"key":"ref27","first-page":"1","article-title":"Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program","author":"rahman","year":"2012","journal-title":"Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing DASIP"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1093\/bib\/bbq015"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1328554.1328565"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2302015"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046222"},{"key":"ref7","article-title":"A systolic array architecture for the smith-waterman algorithm with high performance cell design","author":"laiq","year":"0","journal-title":"2008 IADIS"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/0022-2836(81)90087-5"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2008.46"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"719","DOI":"10.1038\/nature07943","article-title":"The cancer genome","volume":"458","author":"michael","year":"2009","journal-title":"Nature"},{"journal-title":"High-level synthesis of dataflow programs for heterogeneous platforms","year":"2015","author":"bezati","key":"ref20"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2502081.2502231"},{"journal-title":"Orcc","year":"0","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2016.7818352"},{"journal-title":"Xronos","year":"0","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2427278"},{"journal-title":"Vivado High-Level Synthesis","year":"0","key":"ref25"}],"event":{"name":"2017 IEEE International Workshop on Signal Processing Systems (SiPS)","start":{"date-parts":[[2017,10,3]]},"location":"Lorient","end":{"date-parts":[[2017,10,5]]}},"container-title":["2017 IEEE International Workshop on Signal Processing Systems (SiPS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8101043\/8109962\/08109982.pdf?arnumber=8109982","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,6]],"date-time":"2019-10-06T07:50:53Z","timestamp":1570348253000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8109982\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/sips.2017.8109982","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}