{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:38:47Z","timestamp":1761647927279},"reference-count":0,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,6]]},"DOI":"10.1109\/slip.2011.6135439","type":"proceedings-article","created":{"date-parts":[[2012,1,30]],"date-time":"2012-01-30T21:42:55Z","timestamp":1327959775000},"page":"1-1","source":"Crossref","is-referenced-by-count":4,"title":["Performance and power analysis of through silicon via based 3D IC integration"],"prefix":"10.1109","author":[{"given":"Hung Viet","family":"Nguyen","sequence":"first","affiliation":[]},{"given":"Myunghwan","family":"Ryu","sequence":"additional","affiliation":[]},{"given":"Youngmin","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","event":{"name":"2011 International Workshop on System Level Interconnect Prediction (SLIP)","start":{"date-parts":[[2011,6,5]]},"location":"San Diego, CA, USA","end":{"date-parts":[[2011,6,5]]}},"container-title":["International Workshop on System Level Interconnect Prediction"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6125889\/6135427\/06135439.pdf?arnumber=6135439","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T14:53:36Z","timestamp":1490108016000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6135439\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":0,"URL":"https:\/\/doi.org\/10.1109\/slip.2011.6135439","relation":{},"subject":[],"published":{"date-parts":[[2011,6]]}}}