{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T09:00:02Z","timestamp":1725440402481},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,6,6]]},"DOI":"10.1109\/slip.2015.7171711","type":"proceedings-article","created":{"date-parts":[[2015,7,30]],"date-time":"2015-07-30T17:31:28Z","timestamp":1438277488000},"page":"1-8","source":"Crossref","is-referenced-by-count":1,"title":["Power line communication for hybrid power\/signal pin SOC design"],"prefix":"10.1109","author":[{"given":"Xiang","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yang","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryan","family":"Coutts","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chung-kuan","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"33","article-title":"Cacti-3dd: Architecture-level modeling for 3d die-stacked dram main memory","author":"chen","year":"2012","journal-title":"DATE 2012"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593128"},{"year":"0","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228477"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2006.1645753"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665730"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2008.4550119"},{"year":"0","key":"ref2"},{"year":"0","key":"ref9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/EPTC.2008.4763603"}],"event":{"name":"2015 ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","start":{"date-parts":[[2015,6,6]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2015,6,6]]}},"container-title":["2015 ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7160953\/7171703\/07171711.pdf?arnumber=7171711","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T18:48:51Z","timestamp":1490381331000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7171711\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6,6]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/slip.2015.7171711","relation":{},"subject":[],"published":{"date-parts":[[2015,6,6]]}}}