{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,4]],"date-time":"2025-12-04T09:52:57Z","timestamp":1764841977932,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,6,27]]},"DOI":"10.1109\/slip.2017.7974911","type":"proceedings-article","created":{"date-parts":[[2017,7,13]],"date-time":"2017-07-13T16:47:44Z","timestamp":1499964464000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Clock tree synthesis for heterogeneous 3-D integrated circuits"],"prefix":"10.1109","author":[{"given":"Isuru","family":"Daulagala","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ioannis","family":"Savidis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419833"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2003695.2003708"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2010.2099590"},{"key":"ref13","first-page":"651","article-title":"Clock distribution networks for 3-d integrated circuits","author":"pavlidis","year":"2008","journal-title":"Proceedings of the IEEE Custom Integrated Circuits Conference"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2073724"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114920"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/157485.165066"},{"journal-title":"Predictive Technology Model","year":"2002","author":"cao","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514965"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2026200"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1992.227749"},{"key":"ref3","first-page":"569","article-title":"Minimum skew and minimum path length routing in vlsi layout design","volume":"32","author":"edahiro","year":"1991","journal-title":"NEC research& development"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/82.204128"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1992.270316"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1983.1270037"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1995.521489"},{"journal-title":"Three-Dimensional Integrated Circuit Design","year":"2010","author":"pavlidis","key":"ref2"},{"key":"ref1","first-page":"321","article-title":"Tsv-aware 3d physical design tool needs for faster mainstream acceptance of 3d ics","author":"lim","year":"2010","journal-title":"ACM DAC Knowledge Center (dac com)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2008.4484003"}],"event":{"name":"2017 ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","start":{"date-parts":[[2017,6,17]]},"location":"Austin, TX, USA","end":{"date-parts":[[2017,6,17]]}},"container-title":["2017 ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7974634\/7974903\/07974911.pdf?arnumber=7974911","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,8,16]],"date-time":"2017-08-16T12:01:28Z","timestamp":1502884888000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7974911\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,6,27]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/slip.2017.7974911","relation":{},"subject":[],"published":{"date-parts":[[2017,6,27]]}}}