{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,31]],"date-time":"2025-07-31T00:34:00Z","timestamp":1753922040018,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,6]]},"DOI":"10.1109\/smacd.2016.7520725","type":"proceedings-article","created":{"date-parts":[[2016,8,5]],"date-time":"2016-08-05T17:40:44Z","timestamp":1470418844000},"page":"1-4","source":"Crossref","is-referenced-by-count":14,"title":["IIP framework: A tool for reuse-centric analog circuit design"],"prefix":"10.1109","author":[{"given":"Benjamin","family":"Prautsch","sequence":"first","affiliation":[{"name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS, Dresden, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Uwe","family":"Eichler","sequence":"additional","affiliation":[{"name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS, Dresden, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sunil","family":"Rao","sequence":"additional","affiliation":[{"name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS, Dresden, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bjorn","family":"Zeugmann","sequence":"additional","affiliation":[{"name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS, Dresden, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ajith","family":"Puppala","sequence":"additional","affiliation":[{"name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS, Dresden, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Torsten","family":"Reich","sequence":"additional","affiliation":[{"name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS, Dresden, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jens","family":"Lienig","sequence":"additional","affiliation":[{"name":"Dresden University of Technology, Dresden, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691100"},{"year":"0","key":"ref11"},{"key":"ref12","article-title":"Design of a 12-bit Cyclic RSD ADC Sensor Interface IC Using the Intelligent Analog IP Library","author":"reich","year":"2013","journal-title":"ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0232"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923417"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"157","DOI":"10.1023\/A:1021268032124","article-title":"Generation of Technology-Independent Retargetable Analog Blocks","volume":"33","author":"castro-l\u00f3pez","year":"2002","journal-title":"Proc Analog Integrated Circuits and Signal Processing"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ECCTD.2011.6043354"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2269050"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2003.08.004"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2158732"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090670"},{"key":"ref3","article-title":"Analog Synthesis (and Verification) Revisited: Whats's Missing?","author":"rutenbar","year":"2012","journal-title":"Int Conf on Synthesis Modeling Analysis and Simulation Methods and Applications to Circuit Design SMACD"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"75","DOI":"10.1145\/1514932.1514952","article-title":"Constraint-driven Design &#x2013; The Next Step Towards Analog Design Automation","author":"jerke","year":"2009","journal-title":"Proc 2009 Int Symp Phys Design"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2012.6339409"},{"article-title":"Virtuoso Parameterized Cell Reference Product Version 6.1.6","year":"2015","author":"cadence","key":"ref8"},{"key":"ref7","first-page":"1","article-title":"Constraint Propagation Methods for Robust IC Design","author":"krinke","year":"2015","journal-title":"ZuE 2015 8 GMM\/ITG\/GI-Symposium Reliability by Design ZuE"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/5.899053"},{"year":"0","key":"ref9","article-title":"PyCell Studio"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"33","DOI":"10.1145\/2717764.2717781","article-title":"Automation of Analog IC Layout &#x2013; Challenges and Solutions","author":"scheible","year":"2015","journal-title":"Proc Int Symp on Physical Design"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915116"},{"key":"ref22","first-page":"1","article-title":"Abstract Technology Handling for Generator-Based Analog Circuit Design","author":"prautsch","year":"2015","journal-title":"ZuE 2015 8 GMM\/ITG\/GI-Symposium Reliability by Design ZuE"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-4501-6_3"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763267"},{"year":"0","key":"ref23","article-title":"IPLnow"},{"article-title":"UTBB-FDSOI Design & Migration Methodology","year":"0","author":"flatresse","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/4.808896"}],"event":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","start":{"date-parts":[[2016,6,27]]},"location":"Lisbon, Portugal","end":{"date-parts":[[2016,6,30]]}},"container-title":["2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7513177\/7520642\/07520725.pdf?arnumber=7520725","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,5]],"date-time":"2022-07-05T06:19:33Z","timestamp":1657001973000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7520725\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,6]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/smacd.2016.7520725","relation":{},"subject":[],"published":{"date-parts":[[2016,6]]}}}