{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T07:34:14Z","timestamp":1725608054098},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,6]]},"DOI":"10.1109\/smacd.2017.7981563","type":"proceedings-article","created":{"date-parts":[[2017,7,17]],"date-time":"2017-07-17T20:43:57Z","timestamp":1500324237000},"page":"1-4","source":"Crossref","is-referenced-by-count":4,"title":["Comparing code coverage metrics for analog behavioral models"],"prefix":"10.1109","author":[{"given":"Andreas","family":"Furtig","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Moritz","family":"Paschke","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lars","family":"Hedrich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"A path dependency graph for Verilog program analysis","author":"zaki","year":"2003","journal-title":"Proc 1st Northeast Workshop on Circuits and Systems (NEWCAS'03)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429423"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/BF01239381"},{"journal-title":"Epfl-ekv Version 2 6 Verilog-A Implementation","year":"2006","author":"nielsen","key":"ref13"},{"key":"ref4","article-title":"A Practical Tutorial on Modified Condition\/Decision Coverage","author":"kelly j","year":"2001","journal-title":"Tech Rep"},{"key":"ref3","article-title":"Coverage analysis techniques for hdl design validation","author":"jou","year":"1999","journal-title":"Proc Asia Pacific Conf Chip Design Language"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FDL.2016.7880388"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1996.569537"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/UGIM.2003.1225766"},{"key":"ref7","first-page":"115","article-title":"On code coverage measurement for Verilog-A","author":"sha","year":"2004","journal-title":"High-level Design Validation and Test Workshop 2004 Ninth IEEE International"},{"journal-title":"Functional Verification Coverage Measurement and Analysis","year":"2007","author":"piziali","key":"ref2"},{"journal-title":"Software Testing Techniques","year":"1990","author":"beizer","key":"ref1"},{"journal-title":"ADMS Automatic Device Model Synthesizer","year":"0","key":"ref9"}],"event":{"name":"2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","start":{"date-parts":[[2017,6,12]]},"location":"Giardini Naxos, Italy","end":{"date-parts":[[2017,6,15]]}},"container-title":["2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7970054\/7981552\/07981563.pdf?arnumber=7981563","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,8,16]],"date-time":"2017-08-16T16:21:56Z","timestamp":1502900516000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7981563\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,6]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/smacd.2017.7981563","relation":{},"subject":[],"published":{"date-parts":[[2017,6]]}}}