{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,21]],"date-time":"2025-08-21T18:43:27Z","timestamp":1755801807169,"version":"3.44.0"},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,7]]},"DOI":"10.1109\/smacd.2019.8795227","type":"proceedings-article","created":{"date-parts":[[2019,8,15]],"date-time":"2019-08-15T19:22:56Z","timestamp":1565896976000},"page":"33-36","source":"Crossref","is-referenced-by-count":1,"title":["A Structure-Based Methodology for Analog Layout Generation"],"prefix":"10.1109","author":[{"given":"Yu-Hsien","family":"Chen","sequence":"first","affiliation":[{"name":"National Central University, Jung-Li City, Taiwan, ROC"}]},{"given":"Hao-Yu","family":"Chi","sequence":"additional","affiliation":[{"name":"Inst. of Electronics, National Chiao Tung University, Hsin-Chu City, Taiwan, ROC"}]},{"given":"Ling-Yen","family":"Song","sequence":"additional","affiliation":[{"name":"Inst. of Electronics, National Chiao Tung University, Hsin-Chu City, Taiwan, ROC"}]},{"given":"Chien-Nan Jimmy","family":"Liu","sequence":"additional","affiliation":[{"name":"Inst. of Electronics, National Chiao Tung University, Hsin-Chu City, Taiwan, ROC"}]},{"given":"Hung-Ming","family":"Chen","sequence":"additional","affiliation":[{"name":"Inst. of Electronics, National Chiao Tung University, Hsin-Chu City, Taiwan, ROC"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429517"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297370"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923417"},{"key":"ref13","article-title":"LASER - Layout-aware Analog Synthesis Environment on Laker","author":"liao","year":"2013","journal-title":"Proc Great Lakes Symp on VLSI"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2269050"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2158732"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2015.7401683"},{"year":"0","key":"ref17"},{"key":"ref18","article-title":"Layout placement optimization with isolation rings for highvoltage VLSI circuits","author":"lee","year":"2017","journal-title":"Proc VLSI-DAT"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0923"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654239"},{"key":"ref3","first-page":"512","article-title":"Heterogeneous B*-trees for Analog Placement with Symmetry and Regularity Considerations","author":"chou","year":"2011","journal-title":"Proc ICCAD"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160934"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105309"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2012.6164937"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228458"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105379"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090670"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2279516"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICMTS.1996.535615"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2000.838885"}],"event":{"name":"2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","start":{"date-parts":[[2019,7,15]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2019,7,18]]}},"container-title":["2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8786808\/8795217\/08795227.pdf?arnumber=8795227","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,20]],"date-time":"2025-08-20T18:30:35Z","timestamp":1755714635000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8795227\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,7]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/smacd.2019.8795227","relation":{},"subject":[],"published":{"date-parts":[[2019,7]]}}}