{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,31]],"date-time":"2025-07-31T00:45:11Z","timestamp":1753922711439,"version":"3.37.3"},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,6,12]],"date-time":"2022-06-12T00:00:00Z","timestamp":1654992000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,6,12]],"date-time":"2022-06-12T00:00:00Z","timestamp":1654992000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002701","name":"Ministry of Education","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002701","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,6,12]]},"DOI":"10.1109\/smacd55068.2022.9816336","type":"proceedings-article","created":{"date-parts":[[2022,7,11]],"date-time":"2022-07-11T20:02:28Z","timestamp":1657569748000},"page":"1-4","source":"Crossref","is-referenced-by-count":11,"title":["Expert Design Plan: A Toolbox for Procedural Automation of Analog Integrated Circuit Design"],"prefix":"10.1109","author":[{"given":"Matthias","family":"Schweikardt","sequence":"first","affiliation":[{"name":"Reutlingen University,Electronics & Drives,Reutlingen,Germany"}]},{"given":"Juergen","family":"Scheible","sequence":"additional","affiliation":[{"name":"Reutlingen University,Electronics & Drives,Reutlingen,Germany"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2003.1194751"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691100"},{"journal-title":"CMOS Analog Circuit Design","year":"2012","author":"allen","key":"ref10"},{"key":"ref6","first-page":"17","article-title":"A Generic Procedural Generator for Sizing of Analog Integrated Circuits","author":"schweikardt","year":"2019","journal-title":"PrIMe"},{"key":"ref11","first-page":"1","article-title":"Improvement of Simulation-Based Analog Circuit Sizing using Design-Space Transformation","author":"schweikardt","year":"2021","journal-title":"SMACD"},{"key":"ref5","first-page":"1","article-title":"A Procedural Approach to Automate the Manual Design Process in Analog Integrated Circuit Design","author":"leber","year":"2018","journal-title":"Analog"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1017\/9781108125840"},{"journal-title":"Cadence PCell Designer","year":"0","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717781"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006143"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-42037-0"}],"event":{"name":"2022 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","start":{"date-parts":[[2022,6,12]]},"location":"Villasimius, Italy","end":{"date-parts":[[2022,6,15]]}},"container-title":["2022 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9816063\/9816175\/09816336.pdf?arnumber=9816336","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,8]],"date-time":"2022-08-08T20:02:42Z","timestamp":1659988962000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9816336\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,12]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/smacd55068.2022.9816336","relation":{},"subject":[],"published":{"date-parts":[[2022,6,12]]}}}