{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,18]],"date-time":"2025-12-18T14:28:32Z","timestamp":1766068112911,"version":"3.32.0"},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T00:00:00Z","timestamp":1719878400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T00:00:00Z","timestamp":1719878400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,7,2]]},"DOI":"10.1109\/smacd61181.2024.10745436","type":"proceedings-article","created":{"date-parts":[[2024,11,11]],"date-time":"2024-11-11T18:37:50Z","timestamp":1731350270000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["DTCO for Fast STT-MRAM Periphery Operation"],"prefix":"10.1109","author":[{"given":"Ahmed","family":"Hossam-Eldeen","sequence":"first","affiliation":[{"name":"IMEC,Leuven,Belgium"}]},{"given":"Bowen","family":"Wang","sequence":"additional","affiliation":[{"name":"IMEC,Leuven,Belgium"}]},{"given":"Priyanka","family":"Pandey","sequence":"additional","affiliation":[{"name":"IMEC,Leuven,Belgium"}]},{"given":"Marie Garcia","family":"Bardon","sequence":"additional","affiliation":[{"name":"IMEC,Leuven,Belgium"}]},{"given":"Fernando Garcia","family":"Redondo","sequence":"additional","affiliation":[{"name":"IMEC,Leuven,Belgium"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1088\/0022-3727\/46\/13\/139601"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IMW51353.2021.9439592"},{"key":"ref3","doi-asserted-by":"crossref","DOI":"10.1109\/ESSDERC59256.2023.10268481","article-title":"Stt-mram stochastic and defects-aware dtco for last level cache at advanced process nodes","author":"Garc\u013aa-Redondo","year":"2023"},{"key":"ref4","article-title":"Cadence \u00ae spectre \u00ae circuit simulator\/ virtuoso \u00ae layout suite"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.837962"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810048"}],"event":{"name":"2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","start":{"date-parts":[[2024,7,2]]},"location":"Volos, Greece","end":{"date-parts":[[2024,7,5]]}},"container-title":["2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10745284\/10745377\/10745436.pdf?arnumber=10745436","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,9]],"date-time":"2025-01-09T19:31:36Z","timestamp":1736451096000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10745436\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,7,2]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/smacd61181.2024.10745436","relation":{},"subject":[],"published":{"date-parts":[[2024,7,2]]}}}