{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,17]],"date-time":"2026-02-17T12:13:34Z","timestamp":1771330414607,"version":"3.50.1"},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T00:00:00Z","timestamp":1719878400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T00:00:00Z","timestamp":1719878400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,7,2]]},"DOI":"10.1109\/smacd61181.2024.10745444","type":"proceedings-article","created":{"date-parts":[[2024,11,11]],"date-time":"2024-11-11T18:37:50Z","timestamp":1731350270000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["Formal Verification of Nonlinear Analog Circuits using State Space-Based Model Order Reduction"],"prefix":"10.1109","author":[{"given":"Yasmine","family":"Abu-Haeyeh","sequence":"first","affiliation":[{"name":"Institute for Computer Science Goethe University,Frankfurt,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lars","family":"Hedrich","sequence":"additional","affiliation":[{"name":"Institute for Computer Science Goethe University,Frankfurt,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TAC.1981.1102568"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1080\/00207170410001713448"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.806601"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907272"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2421450"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-46520-3_26"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715184"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.384428"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC47756.2020.9045120"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/s10703-009-0086-9"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/UGIM.2003.1225766"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.29007\/zbkv"}],"event":{"name":"2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","location":"Volos, Greece","start":{"date-parts":[[2024,7,2]]},"end":{"date-parts":[[2024,7,5]]}},"container-title":["2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10745284\/10745377\/10745444.pdf?arnumber=10745444","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,11,27]],"date-time":"2024-11-27T14:35:40Z","timestamp":1732718140000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10745444\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,7,2]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/smacd61181.2024.10745444","relation":{},"subject":[],"published":{"date-parts":[[2024,7,2]]}}}