{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T21:12:11Z","timestamp":1725397931139},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,5]]},"DOI":"10.1109\/snpd.2016.7515938","type":"proceedings-article","created":{"date-parts":[[2016,7,26]],"date-time":"2016-07-26T20:38:58Z","timestamp":1469565538000},"page":"443-450","source":"Crossref","is-referenced-by-count":2,"title":["A method for issue queue soft error vulnerability mitigation"],"prefix":"10.1109","author":[{"given":"Liu","family":"Tang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhangqin","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147087"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.20"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310780"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250726"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250725"},{"article-title":"Reducing the Soft Error Rates of a High-Performance Microprocessor Using Front-End Throttling","year":"2006","author":"kalappurakkal","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2008.23"},{"article-title":"Computer architecture: a quantitative approach: Elsevier","year":"2011","author":"hennessy","key":"ref4"},{"key":"ref3","first-page":"129","article-title":"Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics","author":"duan","year":"2009","journal-title":"IEEE International Symposium on High-Performance Comp Architecture"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2004.1311877"},{"key":"ref5","first-page":"99","article-title":"Reservation station architecture for mutable functional unit usage in superscalar processors","author":"solihin","year":"1999","journal-title":"Los Alamos Unclassified Report"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2005.88"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.3390\/ma7010508"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2009.61"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2008.13"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253181"}],"event":{"name":"2016 17th IEEE\/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel\/Distributed Computing (SNPD)","start":{"date-parts":[[2016,5,30]]},"location":"Shanghai, China","end":{"date-parts":[[2016,6,1]]}},"container-title":["2016 17th IEEE\/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel\/Distributed Computing (SNPD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7510515\/7515861\/07515938.pdf?arnumber=7515938","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,23]],"date-time":"2016-09-23T19:40:11Z","timestamp":1474659611000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7515938\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/snpd.2016.7515938","relation":{},"subject":[],"published":{"date-parts":[[2016,5]]}}}