{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T00:00:34Z","timestamp":1729641634328,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/socc.2004.1362416","type":"proceedings-article","created":{"date-parts":[[2004,12,23]],"date-time":"2004-12-23T09:34:02Z","timestamp":1103794442000},"page":"227-230","source":"Crossref","is-referenced-by-count":2,"title":["An efficient error-masking technique for improving the soft-error robustness of static CMOS circuits"],"prefix":"10.1109","author":[{"given":"S.","family":"Krishnamohan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.R.","family":"Mahapatra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253181"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.1999.867224"},{"journal-title":"Digital Integrated Circuits 1st Ed","year":"1996","author":"rabaey","key":"16"},{"key":"13","first-page":"98","article-title":"A standard cell library for student projects","author":"grad","year":"2003","journal-title":"Proc ICMS"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2002.1015084"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/23.903813"},{"key":"12","article-title":"High speed CMOS logic responses to radiation-induced upsets","author":"bernstein","year":"2002","journal-title":"The Designing Robust Circuits and Systems with Unreliable Components Workshop"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766651"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028924"},{"key":"1","first-page":"73","article-title":"Impact of CMOS process scaling and SOI on soft error rates of logical processes","author":"hareland","year":"2001","journal-title":"Symposium on VLSI Technology Digest of Technical Papers"},{"key":"10","doi-asserted-by":"crossref","first-page":"2217","DOI":"10.1109\/23.659038","article-title":"Attenuation of single event induced pulses in CMOS combinational logic","volume":"44","author":"baze","year":"1997","journal-title":"IEEE Transactions on Nuclear Science"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2003.1250141"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/12.862216"},{"key":"5","first-page":"165","article-title":"A novel area-time efficient static CMOS totally self-checking comparator","volume":"28","author":"lo","year":"1993","journal-title":"IEEE JSSC"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2000.840845"},{"key":"9","article-title":"Mitigating single event upsets from combinational logic","author":"hass","year":"1998","journal-title":"Proc 7th NASA Symposium on VLSI Design"},{"key":"8","first-page":"385","article-title":"Latch design for transient pulse tolerance","author":"cha","year":"1994","journal-title":"Proc ACM ICCD"}],"event":{"name":"IEEE International SOC Conference, 2004. Proceedings.","location":"Santa Clara, CA, USA"},"container-title":["IEEE International SOC Conference, 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9408\/29848\/01362416.pdf?arnumber=1362416","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T13:43:30Z","timestamp":1497620610000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1362416\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/socc.2004.1362416","relation":{},"subject":[]}}