{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:31:45Z","timestamp":1729661505484,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,9]]},"DOI":"10.1109\/socc.2008.4641479","type":"proceedings-article","created":{"date-parts":[[2008,10,14]],"date-time":"2008-10-14T15:14:45Z","timestamp":1223997285000},"page":"55-58","source":"Crossref","is-referenced-by-count":0,"title":["Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC"],"prefix":"10.1109","author":[{"family":"Yuejian Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sandy","family":"Thomson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Han Sun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chandra","family":"Bontu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eric","family":"Hall","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1364\/OE.16.000873"},{"key":"2","first-page":"688","article-title":"40 gb\/s optical systems with electronic signal processing","author":"roberts","year":"2007","journal-title":"Proc IEEE\/LEOS Annu Meetings"},{"key":"10","article-title":"giga-scale integration for tera-ops performance: opportunities and new frontiers","author":"gelsinger","year":"2004","journal-title":"Proc 41th Design Automation Conference"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/LEOSST.2007.4288305"},{"key":"7","doi-asserted-by":"crossref","first-page":"203","DOI":"10.1109\/43.743733","article-title":"scan-based bist fault diagnosis","volume":"18","author":"wu","year":"1999","journal-title":"IEEE Trans CAD of Integrated Circuits and Systems"},{"key":"6","first-page":"1","article-title":"accelerated path delay fault simulation","author":"wu","year":"1992","journal-title":"Proc IEEE VLSI Test Symp"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1995.529831"},{"key":"4","first-page":"544","article-title":"a 24gs\/s 6b adc in 90nm cmos","author":"schvan","year":"2008","journal-title":"Proc ISSCC"},{"key":"9","first-page":"63","article-title":"full hold-scan systems in microprocessors: cost\/benefit analysis","volume":"8","author":"kuppuswamy","year":"2004","journal-title":"Intel Technology Journal"},{"key":"8","doi-asserted-by":"crossref","first-page":"327","DOI":"10.1109\/TCAD.2002.807889","article-title":"testing asics with multiple identical cores","volume":"22","author":"wu","year":"2003","journal-title":"IEEE Trans CAD of Integrated Circuits and Systems"}],"event":{"name":"2008 IEEE International SOC Conference (SOCC)","start":{"date-parts":[[2008,9,17]]},"location":"Newport Beach, CA, USA","end":{"date-parts":[[2008,9,20]]}},"container-title":["2008 IEEE International SOC Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4632904\/4641463\/04641479.pdf?arnumber=4641479","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T08:32:25Z","timestamp":1497774745000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4641479\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,9]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/socc.2008.4641479","relation":{},"subject":[],"published":{"date-parts":[[2008,9]]}}}