{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T07:32:57Z","timestamp":1729668777573,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/socc.2010.5784684","type":"proceedings-article","created":{"date-parts":[[2011,6,10]],"date-time":"2011-06-10T11:57:50Z","timestamp":1307707070000},"page":"519-524","source":"Crossref","is-referenced-by-count":1,"title":["Dependable SRAM with enhanced read-\/write-margins by fine-grained assist bias control for low-voltage operation"],"prefix":"10.1109","author":[{"given":"Koji","family":"Nii","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Makoto","family":"Yabuuchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hidehiro","family":"Fujiwara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hirofumi","family":"Nakano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kazuya","family":"Ishihara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroyuki","family":"Kawai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kazutami","family":"Arimoto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"326","article-title":"A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations","author":"m","year":"2007","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"813","DOI":"10.1109\/JSSC.2007.892153","article-title":"An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage","volume":"42","author":"h","year":"2007","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref10","first-page":"219","article-title":"An Embedded Programmable Logic Matrix (ePLX) for flexible functions on SoC","author":"h","year":"2006","journal-title":"Proc IEEE ASSCC Dig Tech Papers"},{"key":"ref6","first-page":"346","article-title":"A 32 nm High-K Metal Gate SRAM with Adaptive Dynamic Stability Enhancement for Low-Voltage Operation","author":"h","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref5","first-page":"212","article-title":"A 45-nm Single-port and Dualport SRAM Family with Robust ReadlWrite Stabilizing Circuitry under DVFS Environment","author":"k","year":"2008","journal-title":"Circuits Digest of Technical Papers Symposium on VLSI"},{"key":"ref8","first-page":"748","article-title":"Static-Noise Marginanalysis of MOS SRAM cells","volume":"sc 22","author":"e","year":"1987","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref7","first-page":"348","article-title":"A Configurable SRAM with Constant-Negative-Level Write Buffer for Low-Voltage Operation with 0.149um2 Cell in 32 nm High-K Metal Gate CMOS","author":"y","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"820","DOI":"10.1109\/JSSC.2007.891648","article-title":"A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits","volume":"42","author":"s","year":"2007","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref9","first-page":"347","article-title":"Variability in sub-100 nm SRAM designs","author":"r","year":"2004","journal-title":"ICCAD Digest"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"705","DOI":"10.1109\/JSSC.2006.869786","article-title":"90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique","volume":"41","author":"m","year":"2006","journal-title":"IEEE Journal of Solid-State Circuits"}],"event":{"name":"2010 IEEE International SOC Conference (SOCC)","start":{"date-parts":[[2010,9,27]]},"location":"Las Vegas, NV, USA","end":{"date-parts":[[2010,9,29]]}},"container-title":["23rd IEEE International SOC Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5755492\/5784634\/05784684.pdf?arnumber=5784684","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T21:25:11Z","timestamp":1497907511000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5784684\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/socc.2010.5784684","relation":{},"subject":[],"published":{"date-parts":[[2010,9]]}}}