{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T06:56:31Z","timestamp":1729666591243,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/socc.2010.5784688","type":"proceedings-article","created":{"date-parts":[[2011,6,10]],"date-time":"2011-06-10T15:57:50Z","timestamp":1307721470000},"page":"330-333","source":"Crossref","is-referenced-by-count":5,"title":["Power minimization methodology for VCTL topologies"],"prefix":"10.1109","author":[{"given":"Osman Kubilay","family":"Ekekon","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Samed","family":"Maltabas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Martin","family":"Margala","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ugur","family":"Cilingiroglu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2003.816365"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"1177","DOI":"10.1109\/4.508266","article-title":"A compact high-speed (31, 5) parallel counter circuit based on capacitive threshold-logic gates","volume":"31","author":"cilingiroglu","year":"1996","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SCS.2003.1227096"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44989-2_88"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1531542.1531600"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2004.1339555"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"1141","DOI":"10.1109\/4.508261","article-title":"A capacitive threshold logic","volume":"31","author":"cilingiroglu","year":"1996","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2004.1339519"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.808446"}],"event":{"name":"2010 IEEE International SOC Conference (SOCC)","start":{"date-parts":[[2010,9,27]]},"location":"Las Vegas, NV, USA","end":{"date-parts":[[2010,9,29]]}},"container-title":["23rd IEEE International SOC Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5755492\/5784634\/05784688.pdf?arnumber=5784688","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T01:25:10Z","timestamp":1497921910000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5784688\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/socc.2010.5784688","relation":{},"subject":[],"published":{"date-parts":[[2010,9]]}}}