{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T14:49:23Z","timestamp":1761662963669},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/socc.2010.5784703","type":"proceedings-article","created":{"date-parts":[[2011,6,10]],"date-time":"2011-06-10T11:57:50Z","timestamp":1307707070000},"page":"392-395","source":"Crossref","is-referenced-by-count":6,"title":["Thermal via planning for temperature reduction in 3D ICs"],"prefix":"10.1109","author":[{"given":"Jin-Tai","family":"Yan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu-Cheng","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhi-Wei","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055171"},{"key":"ref3","first-page":"878","article-title":"3d floorplanning with thermal vias","author":"wong","year":"2006","journal-title":"Design Automation and Test in Europe"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120900"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"ref8","first-page":"209","article-title":"LP base white space redistribution for thermal via planning and performance optimization in 3D ICs","author":"li","year":"2008","journal-title":"Asia and South Pacific Design Automation Conference"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601912"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123048"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/THERMINIC.2008.4669879"},{"key":"ref1","first-page":"745","article-title":"Thermal via planning for 3D ICs","author":"cong","year":"2005","journal-title":"International Conference on Computer-Aided Design"}],"event":{"name":"2010 IEEE International SOC Conference (SOCC)","start":{"date-parts":[[2010,9,27]]},"location":"Las Vegas, NV, USA","end":{"date-parts":[[2010,9,29]]}},"container-title":["23rd IEEE International SOC Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5755492\/5784634\/05784703.pdf?arnumber=5784703","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T02:38:56Z","timestamp":1490063936000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5784703\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/socc.2010.5784703","relation":{},"subject":[],"published":{"date-parts":[[2010,9]]}}}