{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:42:59Z","timestamp":1729622579112,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/socc.2011.6085071","type":"proceedings-article","created":{"date-parts":[[2011,11,23]],"date-time":"2011-11-23T16:54:27Z","timestamp":1322067267000},"page":"30-35","source":"Crossref","is-referenced-by-count":0,"title":["Novel adaptive keeper LBL technique for low power and high performance register files"],"prefix":"10.1109","author":[{"given":"Na","family":"Gong","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Geng","family":"Tang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinhui","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramalingam","family":"Sridhar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","journal-title":"ITRS 2010","key":"13"},{"key":"14","doi-asserted-by":"crossref","first-page":"1149","DOI":"10.1016\/j.mejo.2008.01.028","article-title":"Analysis and optimization of leakage current characteristics in sub-65 nm dual vt footed domino circuits","volume":"39","author":"na","year":"2008","journal-title":"Microelectronics Journal"},{"key":"11","first-page":"19","article-title":"Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation","author":"na","year":"2010","journal-title":"IEEE International SOC Conference"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/TCSI.2011.2107171"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/JSSC.2008.2007150"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1109\/JSSC.2009.2034076"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/ISSCC.2011.5746308"},{"year":"0","journal-title":"PTM Models","key":"10"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/TVLSI.2003.817515"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/VLSIC.2001.934181"},{"key":"5","first-page":"140","article-title":"Issues in dynamic logic design","author":"gronowski","year":"2001","journal-title":"Design of High-Performance Microprocessor Circuits"},{"key":"4","first-page":"505","article-title":"Bit-line organization in register files for low-power and high-performance applications","author":"ataur","year":"2006","journal-title":"International conference on Electrical and Computer Engineering"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1088\/1674-4926\/30\/6\/065005"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/ISCAS.2004.1329422"}],"event":{"name":"2011 IEEE 24th International SOC Conference (SOCC)","start":{"date-parts":[[2011,9,26]]},"location":"Taipei, Taiwan","end":{"date-parts":[[2011,9,28]]}},"container-title":["2011 IEEE International SOC Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6076821\/6085068\/06085071.pdf?arnumber=6085071","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T06:15:21Z","timestamp":1497939321000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6085071\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/socc.2011.6085071","relation":{},"subject":[],"published":{"date-parts":[[2011,9]]}}}