{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T23:05:08Z","timestamp":1729638308221,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,9]]},"DOI":"10.1109\/socc.2012.6398327","type":"proceedings-article","created":{"date-parts":[[2013,1,7]],"date-time":"2013-01-07T14:13:06Z","timestamp":1357567986000},"page":"307-311","source":"Crossref","is-referenced-by-count":1,"title":["Design space exploration for robust power delivery in TSV based 3-D systems-on-chip"],"prefix":"10.1109","author":[{"given":"Suhas M.","family":"Satheesh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emre","family":"Salman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2016614"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2034508"},{"key":"14","doi-asserted-by":"crossref","first-page":"208","DOI":"10.1109\/TCPMT.2010.2101771","article-title":"PDN impedance modeling and analysis of 3d tsv ic by using proposed p\/g tsv array model based on separated p\/g tsv and chip-pdn models","volume":"1","author":"pak","year":"2011","journal-title":"IEEE Trans Comp Packag Manufacturing Technol"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937837"},{"key":"12","first-page":"1","article-title":"TSV modeling and noise coupling in 3d ic","author":"kim","year":"2006","journal-title":"Proc 1st Electron Syst Integration Technol Conf"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/1531542.1531605"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2007.4387161"},{"journal-title":"Three-Dimensional Integrated Circuit Design","year":"2009","author":"pavlidis","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2026200"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/1572471.1572486"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/EPTC.2009.5416531"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2053565"},{"key":"4","doi-asserted-by":"crossref","first-page":"647","DOI":"10.1109\/TVLSI.2009.2038165","article-title":"Power delivery design for 3-d ics using different through-silicon via (tsv) technologies","volume":"19","author":"khan","year":"2011","journal-title":"IEEE Trans on Very Large Scale Integration (VLSI) Systems"},{"key":"9","first-page":"1","article-title":"A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171 ?m2 sram cell size in a 291mb array","author":"natarajan","year":"2008","journal-title":"Proc IEEE Int Electron Device Meeting"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/POLYTR.2007.4339157"}],"event":{"name":"2012 IEEE 25th International SOC Conference (SOCC)","start":{"date-parts":[[2012,9,12]]},"location":"Niagara Falls, NY, USA","end":{"date-parts":[[2012,9,14]]}},"container-title":["2012 IEEE International SOC Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6387373\/6398324\/06398327.pdf?arnumber=6398327","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T01:18:19Z","timestamp":1498007899000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6398327\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,9]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/socc.2012.6398327","relation":{},"subject":[],"published":{"date-parts":[[2012,9]]}}}