{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T14:22:06Z","timestamp":1730298126006,"version":"3.28.0"},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,9]]},"DOI":"10.1109\/socc.2012.6398378","type":"proceedings-article","created":{"date-parts":[[2013,1,7]],"date-time":"2013-01-07T19:13:06Z","timestamp":1357585986000},"page":"45-50","source":"Crossref","is-referenced-by-count":0,"title":["A novel digital loop filter architecture for bang-bang ADPLL"],"prefix":"10.1109","author":[{"given":"Moataz","family":"Abdelfattah","sequence":"first","affiliation":[]},{"given":"Maged","family":"Ghoneima","sequence":"additional","affiliation":[]},{"given":"Yehea I.","family":"Ismail","sequence":"additional","affiliation":[]},{"given":"Amr","family":"Lotfy","sequence":"additional","affiliation":[]},{"given":"Mohamed","family":"Abdelsalam","sequence":"additional","affiliation":[]},{"given":"Mohamed","family":"Abdel-moneum","sequence":"additional","affiliation":[]},{"given":"Nasser A.","family":"Kurd","sequence":"additional","affiliation":[]},{"given":"Greg","family":"Taylor","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162917"},{"key":"2","first-page":"246","article-title":"A tdc-less adpll with 200-to-3200mhz range and 3mw power dissipation for mobile soc clocking in 22nm cmos","author":"august","year":"2012","journal-title":"ISSCC Dig Tech Papers"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910966"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.807398"},{"journal-title":"Theory and Implementation of Digital Bang-bang Frequency Synthesizers for High Speed Serial Data Communications","year":"2007","author":"dalt","key":"6"},{"key":"5","first-page":"2300","article-title":"A 1.35 GHz all-digital fractional-N PLL with adaptive loop gain controller and fractional divider","volume":"45","author":"kim","year":"2010","journal-title":"IEEE J Solid-State Circuits"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831600"},{"key":"8","first-page":"34","article-title":"Designing bang-bang PLLs for clock and data recovery in serial data transmission systems","author":"walker","year":"2003","journal-title":"Phase-Locking in High-Performance Systems"}],"event":{"name":"2012 IEEE 25th International SOC Conference (SOCC)","start":{"date-parts":[[2012,9,12]]},"location":"Niagara Falls, NY, USA","end":{"date-parts":[[2012,9,14]]}},"container-title":["2012 IEEE International SOC Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6387373\/6398324\/06398378.pdf?arnumber=6398378","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T18:35:52Z","timestamp":1490207752000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6398378\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,9]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/socc.2012.6398378","relation":{},"subject":[],"published":{"date-parts":[[2012,9]]}}}