{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T06:19:37Z","timestamp":1729664377059,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/socc.2013.6749658","type":"proceedings-article","created":{"date-parts":[[2014,3,7]],"date-time":"2014-03-07T16:04:09Z","timestamp":1394208249000},"page":"43-48","source":"Crossref","is-referenced-by-count":1,"title":["Layout regularity metric as a fast indicator of high variability circuits"],"prefix":"10.1109","author":[{"given":"Esraa","family":"Swillam","sequence":"first","affiliation":[]},{"given":"Kareem","family":"Madkour","sequence":"additional","affiliation":[]},{"given":"Mohab","family":"Anis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","article-title":"Fast and simple modeling of non-rectangular transistors","author":"wuu","year":"2008","journal-title":"Proc SPIE 7122 Photomask Technology"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1117\/12.814361"},{"year":"2009","author":"scott","journal-title":"Reduction of RTAdriven Intra-die Variation Via Model-based Layout Optimization","key":"11"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1117\/12.630024"},{"key":"3","doi-asserted-by":"crossref","DOI":"10.1117\/12.814701","article-title":"Simplify to Survive, prescriptive layouts ensure profitable scaling to 32nm and beyond","volume":"7275","author":"liebmann","year":"2009","journal-title":"Proc SPIE Design Manufacturing Through Design-Process Integration"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1109\/ICCAD.2004.1382674"},{"year":"2006","author":"tong","journal-title":"Logic Design Regularity for Robust Integrated Circuits","key":"1"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/ASPDAC.2010.5419792"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/DATE.2012.6176581"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1117\/1.2781583"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/VLSIT.2010.5556202"},{"key":"4","doi-asserted-by":"crossref","first-page":"344","DOI":"10.1145\/1278480.1278568","article-title":"exact combinatorial optimization methods for physical design of regular logic bricks","author":"taylor","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/VLSIT.2006.1705271"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/TSM.2007.896638"}],"event":{"name":"2013 IEEE 26th International SoC Conference (SOCC)","start":{"date-parts":[[2013,9,4]]},"location":"Erlangen, Germany","end":{"date-parts":[[2013,9,6]]}},"container-title":["2013 IEEE International SOC Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6745905\/6749643\/06749658.pdf?arnumber=6749658","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T05:14:01Z","timestamp":1498108441000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6749658\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/socc.2013.6749658","relation":{},"subject":[],"published":{"date-parts":[[2013,9]]}}}