{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:27:13Z","timestamp":1725550033068},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/socc.2013.6749713","type":"proceedings-article","created":{"date-parts":[[2014,3,7]],"date-time":"2014-03-07T21:04:09Z","timestamp":1394226249000},"page":"343-348","source":"Crossref","is-referenced-by-count":0,"title":["Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module"],"prefix":"10.1109","author":[{"given":"Seung Mo","family":"Jung","sequence":"first","affiliation":[]},{"given":"Jong Hyun","family":"Seok","sequence":"additional","affiliation":[]},{"given":"Ho Jin","family":"Yoo","sequence":"additional","affiliation":[]},{"given":"Do Hyung","family":"Kim","sequence":"additional","affiliation":[]},{"given":"You Keun","family":"Han","sequence":"additional","affiliation":[]},{"given":"Woo Seop","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Joo Sun","family":"Choi","sequence":"additional","affiliation":[]},{"given":"Jun Dong","family":"Cho","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"0","key":"3"},{"year":"0","key":"2"},{"key":"10","article-title":"Enhancing signal integrity through a low-overhead encoding scheme on address buses","author":"tiehan","year":"2003","journal-title":"Design Automation and Test in Europe Conference and Exhibition"},{"journal-title":"Managing Signal Integrity [PCB Design]","year":"1994","author":"goyal","key":"1"},{"journal-title":"Digital Timing Measurements From Scopes And Probes to Timing And Jitter","year":"2006","author":"wolfgang","key":"7"},{"key":"6","first-page":"235","author":"brooks","year":"2003","journal-title":"Signal Integrity Issues and Printed Circuit Board Design"},{"year":"0","key":"5"},{"journal-title":"Semiconductor Module Includes Semiconductor Chip Initialized by Reset Signal","year":"2012","author":"nishio","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3640-3"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/EDAPS.2011.6213774"},{"key":"11","article-title":"Crosstalk cancellation of ddr3 memory channel for over 1600 mbps data rate","author":"junwoo","year":"2009","journal-title":"17th Int Zurich Symposium on Electromagnetic Compatibility"}],"event":{"name":"2013 IEEE 26th International SoC Conference (SOCC)","start":{"date-parts":[[2013,9,4]]},"location":"Erlangen, Germany","end":{"date-parts":[[2013,9,6]]}},"container-title":["2013 IEEE International SOC Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6745905\/6749643\/06749713.pdf?arnumber=6749713","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T21:47:48Z","timestamp":1490305668000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6749713\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/socc.2013.6749713","relation":{},"subject":[],"published":{"date-parts":[[2013,9]]}}}