{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,6]],"date-time":"2026-03-06T19:00:37Z","timestamp":1772823637404,"version":"3.50.1"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/socc.2014.6948959","type":"proceedings-article","created":{"date-parts":[[2014,11,12]],"date-time":"2014-11-12T17:41:20Z","timestamp":1415814080000},"page":"383-389","source":"Crossref","is-referenced-by-count":38,"title":["Memristor crossbar based multicore neuromorphic processors"],"prefix":"10.1109","author":[{"given":"Tarek M.","family":"Taha","sequence":"first","affiliation":[]},{"given":"Raqibul","family":"Hasan","sequence":"additional","affiliation":[]},{"given":"Chris","family":"Yakopcic","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-7597-2_15"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2008.4687366"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2252057"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1038\/nature06932"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272559"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2012.2195725"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055294"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2012.6252637"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2010.5596751"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722187"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2009.5179043"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1364\/AO.49.000B83"},{"key":"10","first-page":"29","article-title":"High-performance computing for systems of spiking neurons","volume":"2","author":"furber","year":"2006","journal-title":"Proc AISB'06 workshop on GC5 Architecture of Brain and Mind"},{"key":"7","article-title":"Towards neural acceleration for general-purpose approximate computing","author":"esmaeilzadeh","year":"2012","journal-title":"Workshop on Energy-Efficient Design"},{"key":"6","article-title":"Neural acceleration for general-purpose approximate programs","author":"esmaeilzadeh","year":"2012","journal-title":"International Symposium on Microarchitecture (MICRO)"},{"key":"5","article-title":"Recognition, mining and synthesis moves computers to the era of tera","author":"dubey","year":"2005","journal-title":"Technology Intel Magazine"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2012.6402898"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1693639"},{"key":"8","article-title":"Wafer-scale integration of analog neural networks","author":"schemmel","year":"2008","journal-title":"IEEE International Joint Conference on Neural Networks (IJCNN)"}],"event":{"name":"2014 27th IEEE International System-on-Chip Conference (SOCC)","location":"Las Vegas, NV, USA","start":{"date-parts":[[2014,9,2]]},"end":{"date-parts":[[2014,9,5]]}},"container-title":["2014 27th IEEE International System-on-Chip Conference (SOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6937053\/6948870\/06948959.pdf?arnumber=6948959","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T00:49:01Z","timestamp":1490316541000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6948959\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/socc.2014.6948959","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}