{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:45:35Z","timestamp":1761648335517,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/socc.2015.7406952","type":"proceedings-article","created":{"date-parts":[[2016,3,27]],"date-time":"2016-03-27T22:08:48Z","timestamp":1459116528000},"page":"231-234","source":"Crossref","is-referenced-by-count":6,"title":["A digital background calibration technique for split DAC based SAR ADC by using redundant cycle"],"prefix":"10.1109","author":[{"given":"Wuguang","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rulin","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guoquan","family":"Sun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Weijun","family":"Mao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaolei","family":"Zhu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"145","article-title":"A 9b 100MS\/s 1.46mW SARADC in 65nm CMOS","author":"chen","year":"2009","journal-title":"IEEE ASSCC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280859"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2013.6649084"},{"key":"ref6","first-page":"1316","article-title":"A 12-bit 1-msample\/s capacitor error-averaging A\/D converter","volume":"33","author":"song","year":"1988","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052233"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052231"},{"key":"ref7","first-page":"384","article-title":"A 10b 50 MS\/s 820 &#x00B5;W SAR ADC with on-chipdigital calibration","author":"yoshioka","year":"2010","journal-title":"IEEE ISSCC 2010 Dig Tech Papers"},{"key":"ref2","first-page":"196","article-title":"A 0.85fJ\/conversion-step 10b 200KS\/s Subranging SAR ADC in 40nm CMOS","author":"tai","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref9","first-page":"380","article-title":"A 12b 22.5\/45MS\/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR","author":"liu","year":"2010","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E95.C.1026"}],"event":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","start":{"date-parts":[[2015,9,8]]},"location":"Beijing, China","end":{"date-parts":[[2015,9,11]]}},"container-title":["2015 28th IEEE International System-on-Chip Conference (SOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7363404\/7406870\/07406952.pdf?arnumber=7406952","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T18:05:07Z","timestamp":1490205907000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7406952\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/socc.2015.7406952","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}