{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,29]],"date-time":"2026-04-29T07:26:17Z","timestamp":1777447577329,"version":"3.51.4"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1109\/socc.2017.8226004","type":"proceedings-article","created":{"date-parts":[[2017,12,22]],"date-time":"2017-12-22T01:01:14Z","timestamp":1513904474000},"page":"45-50","source":"Crossref","is-referenced-by-count":3,"title":["A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications"],"prefix":"10.1109","author":[{"given":"Mahesh Kumar","family":"Adimulam","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Krishna Kumar","family":"Movva","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.B","family":"Srinivas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"929","DOI":"10.1109\/TCSI.2016.2546856","article-title":"A 12-bit 210-MS\/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique","volume":"63","author":"chin-yu","year":"2016","journal-title":"IEEE Transactions on Circuits and Systems I Regular Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2050937"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2222837"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"1585","DOI":"10.1109\/JSSC.2011.2143870","article-title":"A 26 ?W 8 bit 10 MS\/s Asynchronous SAR ADC for Low Energy Radios","volume":"46","author":"pieter ja","year":"2011","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"2285","DOI":"10.1109\/TCSI.2013.2246206","article-title":"A 4-bit, 1.6 GS\/s low power flash ADC, based on offset calibration and segmentation","volume":"60","author":"mohammad","year":"2013","journal-title":"IEEE Transactions on Circuits and Systems I Regular Papers"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"1433","DOI":"10.1109\/JSSC.1989.572629","article-title":"Matching properties of MOS transistors","volume":"24","author":"marcel jm","year":"1989","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"837","DOI":"10.1109\/TCSII.2011.2168020","article-title":"A 1.5-GS\/s flash ADC With 57.7-dB SFDR and 6.4-bit ENOB in 90 nm digital CMOS","volume":"58","author":"jorge","year":"2011","journal-title":"IEEE Transactions on Circuits and Systems II Express Briefs"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"2901","DOI":"10.1109\/JSSC.2015.2463094","article-title":"A 1 mW71.5 dB SNDR50MS\/s 13 bit fully differential ring amplifier based SAR-assisted pipeline ADC","volume":"50","author":"yong","year":"2015","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"354","DOI":"10.1109\/TVLSI.2016.2576468","article-title":"A 10-bit 500-MS\/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations","volume":"25","author":"yan","year":"2017","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"1381","DOI":"10.1109\/TCSI.2016.2580703","article-title":"A 14-bit 250 MS\/s IF sampling pipelined ADC in 180 nm CMOS process","volume":"63","author":"xuqiang","year":"2016","journal-title":"IEEE Transactions on Circuits and Systems I Regular Papers"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"1592","DOI":"10.1109\/JSSC.2015.2436875","article-title":"A 12 b 53 mW 195 MS\/s pipeline ADC with 82 dB SFDR using split-ADC calibration","volume":"50","author":"rohan","year":"2015","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/TCSI.2014.2349571","article-title":"A 0.3 V 10-bit 1.17 f SAR ADC with merge and split switching in 90 nm CMOS","volume":"62","author":"jin-yi","year":"2015","journal-title":"IEEE Transactions on Circuits and Systems I Regular Papers"},{"key":"ref5","article-title":"A 5.5 fJ\/conv-step 6.4 MS\/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme","author":"ming","year":"2015","journal-title":"Solid-State Circuits Conference-(ISSCC) 2015 IEEE International"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"562","DOI":"10.1109\/TCSI.2016.2613505","article-title":"A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS","volume":"64","author":"jin-yi","year":"2017","journal-title":"IEEE Transactions on Circuits and Systems I Regular Papers"},{"key":"ref7","article-title":"A 76nW, 4kS\/s 10-bit SAR ADC with offset cancellation for biomedical applications","author":"manuel","year":"2016","journal-title":"Circuits and Systems (APCCAS) 2016 IEEE Asia Pacific Conference on"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"2688","DOI":"10.1109\/JSSC.2007.908760","article-title":"A 10-bit 205MS\/s 1.0-mm 2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications","volume":"42","author":"seung-chul","year":"2007","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref1","first-page":"2319","article-title":"A 65 nm CMOS 7b 2 GS\/s 20.7 mW flash ADC with cascaded latch interpolation","volume":"10","author":"jong-in","year":"2015","journal-title":"IEEE J Solid State Circuits"},{"key":"ref9","article-title":"A 12b 50MS\/s 3.5 mW SAR assisted 2-stage pipeline ADC","year":"2010","journal-title":"VLSI Circuits (VLSIC) 2010 IEEE Symposium on"}],"event":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","location":"Munich","start":{"date-parts":[[2017,9,5]]},"end":{"date-parts":[[2017,9,8]]}},"container-title":["2017 30th IEEE International System-on-Chip Conference (SOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8170502\/8225969\/08226004.pdf?arnumber=8226004","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,8]],"date-time":"2019-10-08T12:43:28Z","timestamp":1570538608000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8226004\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/socc.2017.8226004","relation":{},"subject":[],"published":{"date-parts":[[2017,9]]}}}