{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,18]],"date-time":"2026-01-18T09:23:31Z","timestamp":1768728211320,"version":"3.49.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/socc.2018.8618565","type":"proceedings-article","created":{"date-parts":[[2019,1,22]],"date-time":"2019-01-22T07:02:38Z","timestamp":1548140558000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["On a New Hardware Trojan Attack on Power Budgeting of Many Core Systems"],"prefix":"10.1109","author":[{"given":"Yiming","family":"Zhao","sequence":"first","affiliation":[]},{"given":"Xiaohang","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Yingtao","family":"Jiang","sequence":"additional","affiliation":[]},{"given":"Yang","family":"Mei","sequence":"additional","affiliation":[]},{"given":"Amit Kumar","family":"Singh","sequence":"additional","affiliation":[]},{"given":"Terrence","family":"Mak","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"136","DOI":"10.1016\/j.micpro.2016.03.006","article-title":"A pareto-optimal runtime power budgeting scheme for many-core systems","volume":"46","author":"wang","year":"2016","journal-title":"Microprocessors and Microsystems"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"145","DOI":"10.1145\/2654822.2541962","article-title":"Ref: resource elasticity fairness with sharing incentives for multiprocessors","volume":"42","author":"zahedi","year":"2014","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370821"},{"key":"ref13","article-title":"Advancing the state-of-the-art in hardware trojans design","author":"haider","year":"2016","journal-title":"Arxiv preprint arXiv"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3058060.3058061"},{"key":"ref15","first-page":"18:1","article-title":"Memory performance attacks: denial of memory service in multi-core systems","author":"moscibroda","year":"2007","journal-title":"Proc USENIX Security07"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2016.06.008"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2017.8016142"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2016.59"},{"key":"ref19","first-page":"899","article-title":"Reducing packet dropping in a bufferless noc","author":"g\u00f3mez","year":"2008","journal-title":"Proc European Conf Parallel Processing"},{"key":"ref4","first-page":"1","article-title":"Invited-who is the major threat to tomorrows security?: You, the hardware designer","author":"burleson","year":"2016","journal-title":"Proc Design Automation Conf"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2016.01.004"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2954679.2872382"},{"key":"ref5","first-page":"155:1","article-title":"Shift sprinting: fine-grained temperature-aware noc-based mcsoc architecture in dark silicon age","author":"rezaei","year":"2016","journal-title":"Proc Design Automation Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.026"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370828"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2016.7479228"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2930670"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2506565"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495568"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2544375.2544393"},{"key":"ref21","first-page":"1","article-title":"De-signing and implementing malicious hardware","volume":"8","author":"king","year":"2008","journal-title":"Proc Large-Scale Exploits and Emergent Threats"}],"event":{"name":"2018 31st IEEE International System-on-Chip Conference (SOCC)","location":"Arlington, VA","start":{"date-parts":[[2018,9,4]]},"end":{"date-parts":[[2018,9,7]]}},"container-title":["2018 31st IEEE International System-on-Chip Conference (SOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8600278\/8618478\/08618565.pdf?arnumber=8618565","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T23:59:06Z","timestamp":1643241546000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8618565\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/socc.2018.8618565","relation":{},"subject":[],"published":{"date-parts":[[2018,9]]}}}