{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T15:17:46Z","timestamp":1759331866008,"version":"3.41.2"},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,9]]},"DOI":"10.1109\/socc46988.2019.1570548362","type":"proceedings-article","created":{"date-parts":[[2020,5,7]],"date-time":"2020-05-07T21:27:28Z","timestamp":1588886848000},"page":"284-288","source":"Crossref","is-referenced-by-count":3,"title":["A 2.7-Gb\/s Clock and Data Recovery Circuit Based on D\/PLL"],"prefix":"10.1109","author":[{"given":"You-Sheng","family":"Lin","sequence":"first","affiliation":[{"name":"National Chung Hsing University,Department of Electrical Engineering,145 Xingda Rd., South Dist., Taichung City 402,Taiwan (R.O.C.)"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Miao-Shan","family":"Li","sequence":"additional","affiliation":[{"name":"National Chung Hsing University,Department of Electrical Engineering,145 Xingda Rd., South Dist., Taichung City 402,Taiwan (R.O.C.)"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ching-Yuan","family":"Yang","sequence":"additional","affiliation":[{"name":"National Chung Hsing University,Department of Electrical Engineering,145 Xingda Rd., South Dist., Taichung City 402,Taiwan (R.O.C.)"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.808920"},{"key":"ref3","first-page":"1728","article-title":"A 2.4-GHz Fractional-N PLL with a PFD\/CP Linearization and an Improved CP Circuit","author":"ti","year":"2008","journal-title":"Proc Int Symp Circuits Syst (ISCAS)"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"760","DOI":"10.1109\/4.568848","article-title":"A Fully Integrated Low-Noise 1-GHz Frequency Synthesizer Design for Mobile Communication Application","volume":"32","author":"lee","year":"1997","journal-title":"IEEE J Sold-State Circuits"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.856577"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.173100"}],"event":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","start":{"date-parts":[[2019,9,3]]},"location":"Singapore","end":{"date-parts":[[2019,9,6]]}},"container-title":["2019 32nd IEEE International System-on-Chip Conference (SOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9083732\/9087941\/09088099.pdf?arnumber=9088099","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,28]],"date-time":"2025-07-28T19:44:35Z","timestamp":1753731875000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9088099\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,9]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/socc46988.2019.1570548362","relation":{},"subject":[],"published":{"date-parts":[[2019,9]]}}}