{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,29]],"date-time":"2026-04-29T14:51:51Z","timestamp":1777474311771,"version":"3.51.4"},"reference-count":26,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,9]]},"DOI":"10.1109\/socc46988.2019.1570558011","type":"proceedings-article","created":{"date-parts":[[2020,5,7]],"date-time":"2020-05-07T21:27:28Z","timestamp":1588886848000},"page":"21-26","source":"Crossref","is-referenced-by-count":4,"title":["RCAS: Critical Load Based Ranking for Efficient Channel Allocation in Wireless NoC"],"prefix":"10.1109","author":[{"given":"Sidhartha Sankar","family":"Rout","sequence":"first","affiliation":[{"name":"Indraprastha Institute of Information Technology Delhi,New Delhi,India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vaibhav Ishwarlal","family":"Chaudhari","sequence":"additional","affiliation":[{"name":"Indraprastha Institute of Information Technology Delhi,New Delhi,India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Suyog Bhimrao","family":"Patil","sequence":"additional","affiliation":[{"name":"Indraprastha Institute of Information Technology Delhi,New Delhi,India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sujay","family":"Deb","sequence":"additional","affiliation":[{"name":"Indraprastha Institute of Information Technology Delhi,New Delhi,India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.176"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea5020038"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.4108\/ICST.NANONET2007.2139"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.98"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2018.00028"},{"key":"ref15","first-page":"1052","article-title":"Latency criticality aware on-chip communication","author":"li","year":"2009","journal-title":"2009 Design, Automation & Test in Europe Conference & Exhibition"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555801"},{"key":"ref17","first-page":"176","article-title":"Organizing the last line of defense before hitting the memory wall for cmps","author":"liu","year":"2004","journal-title":"10th International Symposium on High Performance Computer Architecture (HPCA 04)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351698"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DCIS.2018.8681475"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2018.8357293"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2016.7479205"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2011.37"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2193835"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771803"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.224"},{"key":"ref2","first-page":"23:1","article-title":"On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches","volume":"12","author":"lee","year":"2008","journal-title":"ACM Trans Des Autom Electron Syst"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2013.6749716"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2018.00113"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.42"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1016\/j.sysarc.2003.07.004","article-title":"Qnoc: Qos architecture and design process for network on chip","volume":"50","author":"bolotin","year":"2004","journal-title":"J Syst Archit"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2953878"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2018.8512164"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2014.2299539"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"}],"event":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","location":"Singapore","start":{"date-parts":[[2019,9,3]]},"end":{"date-parts":[[2019,9,6]]}},"container-title":["2019 32nd IEEE International System-on-Chip Conference (SOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9083732\/9087941\/09088091.pdf?arnumber=9088091","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,20]],"date-time":"2025-08-20T18:40:00Z","timestamp":1755715200000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9088091\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,9]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/socc46988.2019.1570558011","relation":{},"subject":[],"published":{"date-parts":[[2019,9]]}}}