{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,2]],"date-time":"2026-01-02T07:34:46Z","timestamp":1767339286804,"version":"3.35.0"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,9,8]],"date-time":"2020-09-08T00:00:00Z","timestamp":1599523200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,9,8]],"date-time":"2020-09-08T00:00:00Z","timestamp":1599523200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,9,8]]},"DOI":"10.1109\/socc49529.2020.9524762","type":"proceedings-article","created":{"date-parts":[[2021,9,6]],"date-time":"2021-09-06T21:38:32Z","timestamp":1630964312000},"page":"7-12","source":"Crossref","is-referenced-by-count":2,"title":["A Reconfigurable Permutation Based Address Encryption Architecture for Memory Security"],"prefix":"10.1109","author":[{"given":"Yuchen","family":"Mei","sequence":"first","affiliation":[{"name":"School of Electronic Science and Engineering, Nanjing University,Nanjing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Li","family":"Du","sequence":"additional","affiliation":[{"name":"School of Electronic Science and Engineering, Nanjing University,Nanjing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuewen","family":"He","sequence":"additional","affiliation":[{"name":"School of Electronic Science and Engineering, Nanjing University,Nanjing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan","family":"Du","sequence":"additional","affiliation":[{"name":"School of Electronic Science and Engineering, Nanjing University,Nanjing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoliang","family":"Chen","sequence":"additional","affiliation":[{"name":"School of Electronic Science and Engineering, Nanjing University,Nanjing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhongfeng","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Electronic Science and Engineering, Nanjing University,Nanjing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCIT.2019.8905235"},{"key":"ref11","first-page":"175","article-title":"220mv-900mv 794\/584\/754gbps\/w reconfigurable gf (2 4) 2 aes\/sms4\/camellia symmetric-key cipher accelerator in 14nm tri-gate cmos","author":"satpathy","year":"0","journal-title":"2018 IEEE Symposium on VLSI Circuits"},{"key":"ref12","article-title":"Apparatus and method for memory address encryption","author":"gammel","year":"2019","journal-title":"US Patent"},{"journal-title":"Address scrambling in a semiconductor memory","year":"1999","author":"wong","key":"ref13"},{"journal-title":"Address encryption method for flash memories","year":"2009","author":"feuser","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1049\/cje.2015.07.013"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.84"},{"journal-title":"Bit permutation instructions Architecture implementation and cryptographic properties","year":"2004","author":"jerry shi","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878264"},{"key":"ref19","first-page":"484","article-title":"Functional encryption of integrated circuits by key-based hybrid obfuscation","author":"sandhya","year":"0","journal-title":"2017 51st Asilomar Conference on Signals Systems and Computers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/356989.357005"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2566673"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"570","DOI":"10.1109\/MDT.2007.179","article-title":"Aegis: A single-chip secure processor","volume":"24","author":"edward suh","year":"2007","journal-title":"IEEE Design & Test of Computers"},{"key":"ref5","first-page":"357","article-title":"Aegis: architecture for tamper-evident and tamper-resistant processing","author":"edward suh","year":"0","journal-title":"ACM International Conference on Supercomputing 25th Anniversary Volume"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702450"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.16"},{"journal-title":"A Memory Encryption Engine Suitable for General Purpose Processors","year":"2016","author":"gueron","key":"ref2"},{"key":"ref1","article-title":"Amd memory encryption","author":"kaplan","year":"2016","journal-title":"White Paper"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TrustCom\/BigDataSE.2018.00204"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/INDCON.2012.6420811"}],"event":{"name":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","start":{"date-parts":[[2020,9,8]]},"location":"Las Vegas, NV, USA","end":{"date-parts":[[2020,9,11]]}},"container-title":["2020 IEEE 33rd International System-on-Chip Conference (SOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9524739\/9524720\/09524762.pdf?arnumber=9524762","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,30]],"date-time":"2025-01-30T19:13:30Z","timestamp":1738264410000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9524762\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,8]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/socc49529.2020.9524762","relation":{},"subject":[],"published":{"date-parts":[[2020,9,8]]}}}