{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,16]],"date-time":"2026-06-16T05:22:07Z","timestamp":1781587327599,"version":"3.54.5"},"reference-count":44,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T00:00:00Z","timestamp":1759104000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T00:00:00Z","timestamp":1759104000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,9,29]]},"DOI":"10.1109\/socc66126.2025.11235352","type":"proceedings-article","created":{"date-parts":[[2025,11,17]],"date-time":"2025-11-17T18:39:03Z","timestamp":1763404743000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["Large Language Models (LLMs) for Electronic Design Automation (EDA) : Special Session Paper"],"prefix":"10.1109","author":[{"given":"Kangwei","family":"Xu","sequence":"first","affiliation":[{"name":"Technical University of Munich"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Denis","family":"Schwachhofer","sequence":"additional","affiliation":[{"name":"University of Stuttgart"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jason","family":"Blocklove","sequence":"additional","affiliation":[{"name":"New York University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ilia","family":"Polian","sequence":"additional","affiliation":[{"name":"University of Stuttgart"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Peter","family":"Domanski","sequence":"additional","affiliation":[{"name":"University of Stuttgart"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dirk","family":"Pfl\u00fcger","sequence":"additional","affiliation":[{"name":"University of Stuttgart"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Siddharth","family":"Garg","sequence":"additional","affiliation":[{"name":"New York University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ramesh","family":"Karri","sequence":"additional","affiliation":[{"name":"New York University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ozgur","family":"Sinanoglu","sequence":"additional","affiliation":[{"name":"New York University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Johann","family":"Knechtel","sequence":"additional","affiliation":[{"name":"New York University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhuorui","family":"Zhao","sequence":"additional","affiliation":[{"name":"Technical University of Munich"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ulf","family":"Schlichtmann","sequence":"additional","affiliation":[{"name":"Technical University of Munich"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bing","family":"Li","sequence":"additional","affiliation":[{"name":"University of Siegen"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2022.3216799"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD58807.2023.10299874"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/mlcad62225.2024.10740247"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137086"},{"key":"ref5","article-title":"Large Language Models for Verification, Testing, and Design","author":"Jha","year":"2025","journal-title":"ETS"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/iseda65950.2025.11100410"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3723876"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323953"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/LAD62341.2024.10691811"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676730"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3530775"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3663517"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED65160.2025.11014398"},{"key":"ref14","article-title":"VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning","author":"Zhao","year":"2025","journal-title":"SOCC"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3657353"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3734524"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/mlcad62225.2024.10740250"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/DATE64628.2025.10992873"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/LAD62341.2024.10691792"},{"key":"ref20","article-title":"Using LLMs to Facilitate Formal Verification of RTL","author":"Orenes-Vera","year":"2023"},{"key":"ref21","article-title":"LLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting","author":"Huang","year":"2024","journal-title":"ASP-DAC"},{"key":"ref22","article-title":"Advanced LLM-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis","author":"Thorat","year":"2023"},{"key":"ref23","article-title":"VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs","author":"Tasnia","year":"2025","journal-title":"ICCAD"},{"key":"ref24","article-title":"MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization","author":"Wang","year":"2025"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2025.3529805"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3749986"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/mlcad62225.2024.10740262"},{"key":"ref28","article-title":"HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis","author":"Xu","year":"2025","journal-title":"ICCAD"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ATS49688.2020.9301557"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-DAT.2018.8373238"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ETS56758.2023.10173985"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ETS61313.2024.10567817"},{"key":"ref33","article-title":"SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine","author":"Zhao","year":"2020","journal-title":"Fourth Workshop on Computer Architecture Research with RISC-V"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/DFT63277.2024.10753556"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/3690635"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3380446.3430634"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/3643681"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2024.3483089"},{"key":"ref39","article-title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","author":"Liu","year":"2023","journal-title":"ICCAD"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2025.3604320"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI61997.2024.00076"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ICLAD65226.2025.00018"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.23919\/DATE64628.2025.10993260"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD65511.2025.11189152"}],"event":{"name":"2025 IEEE 38th International System-on-Chip Conference (SOCC)","location":"Dubai, United Arab Emirates","start":{"date-parts":[[2025,9,29]]},"end":{"date-parts":[[2025,10,1]]}},"container-title":["2025 IEEE 38th International System-on-Chip Conference (SOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11235309\/11235311\/11235352.pdf?arnumber=11235352","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,3]],"date-time":"2026-02-03T20:51:16Z","timestamp":1770151876000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11235352\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,9,29]]},"references-count":44,"URL":"https:\/\/doi.org\/10.1109\/socc66126.2025.11235352","relation":{},"subject":[],"published":{"date-parts":[[2025,9,29]]}}}