{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T06:31:02Z","timestamp":1763447462891,"version":"3.45.0"},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T00:00:00Z","timestamp":1759104000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T00:00:00Z","timestamp":1759104000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,9,29]]},"DOI":"10.1109\/socc66126.2025.11235402","type":"proceedings-article","created":{"date-parts":[[2025,11,17]],"date-time":"2025-11-17T18:39:03Z","timestamp":1763404743000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Performance Impact of Caches, Interrupt Strategies and Communication on SoC Lookaside Acceleration"],"prefix":"10.1109","author":[{"given":"Alperen","family":"Bolat","sequence":"first","affiliation":[{"name":"Queen&#x2019;s University Belfast,Belfast,UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sakir","family":"Sezer","sequence":"additional","affiliation":[{"name":"Queen&#x2019;s University Belfast,Belfast,UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kieran","family":"Mclaughlin","sequence":"additional","affiliation":[{"name":"Queen&#x2019;s University Belfast,Belfast,UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Henry","family":"Hui","sequence":"additional","affiliation":[{"name":"Queen&#x2019;s University Belfast,Belfast,UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fatih","family":"Kurugollu","sequence":"additional","affiliation":[{"name":"University of Sharjah,Sharjah,UAE"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358271"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3229631.3229651"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3505139"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/s12243-023-00994-3"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1117\/12.771651"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2018.8579304"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC58585.2023.10257113"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844485"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-27609-5_14"},{"key":"ref10","article-title":"Xilinx Zynq MPSoC Zedboard"},{"key":"ref11","article-title":"ARM Cortex-A9 Processor"}],"event":{"name":"2025 IEEE 38th International System-on-Chip Conference (SOCC)","start":{"date-parts":[[2025,9,29]]},"location":"Dubai, United Arab Emirates","end":{"date-parts":[[2025,10,1]]}},"container-title":["2025 IEEE 38th International System-on-Chip Conference (SOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11235309\/11235311\/11235402.pdf?arnumber=11235402","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T06:26:27Z","timestamp":1763447187000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11235402\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,9,29]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/socc66126.2025.11235402","relation":{},"subject":[],"published":{"date-parts":[[2025,9,29]]}}}