{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:42:06Z","timestamp":1729622526707,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,9]]},"DOI":"10.1109\/soccon.2009.5398020","type":"proceedings-article","created":{"date-parts":[[2010,1,26]],"date-time":"2010-01-26T17:38:06Z","timestamp":1264527486000},"page":"365-368","source":"Crossref","is-referenced-by-count":0,"title":["Variation aware low power buffered interconnect design"],"prefix":"10.1109","author":[{"given":"Ashok","family":"Narasimhan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramalingam","family":"Sridhar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1998.705287"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/16.75219"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/16.249433"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1989.77002"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/43.331409"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"648","DOI":"10.1109\/ISQED.2005.10","article-title":"A more effective cEFF","author":"nassif","year":"2005","journal-title":"Proc International Symposium on Quality of Electronic Design"},{"key":"ref16","first-page":"201","article-title":"New paradigm of predictive MOSFET and interconnect modeling for early circuit design","author":"cao","year":"2000","journal-title":"Proceedings of the IEEE CICC Conference"},{"key":"ref17","first-page":"193","article-title":"The impact of back-end-of-line process variations on critical path timing","author":"hoang","year":"2006","journal-title":"Proc IEEE Interconnects Technology Conf"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.863750"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159739"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.2001.954689"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"1515","DOI":"10.1109\/81.886981","article-title":"Uniform repeater insertion in RC trees","volume":"47","author":"adler","year":"2000","journal-title":"IEEE Trans Circuits and Systems I"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1996.541910"},{"key":"ref7","first-page":"131","article-title":"A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations","author":"wason","year":"2005","journal-title":"Proc International Symposium on Low Power Electronics and Design (ISLPED)"},{"article-title":"Circuits, Interconnections and Packaging for VLSI","year":"1990","author":"bakoglu","key":"ref2"},{"year":"2008","key":"ref1","article-title":"International Technology Roadmap for Semiconductors"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.658636"}],"event":{"name":"2009 IEEE International SOC Conference (SOCC)","start":{"date-parts":[[2009,9,9]]},"location":"Belfast, Northern Ireland","end":{"date-parts":[[2009,9,11]]}},"container-title":["2009 IEEE International SOC Conference (SOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5379508\/5397993\/05398020.pdf?arnumber=5398020","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T04:06:28Z","timestamp":1497845188000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5398020\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,9]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/soccon.2009.5398020","relation":{},"subject":[],"published":{"date-parts":[[2009,9]]}}}