{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T03:44:41Z","timestamp":1725594281407},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,9]]},"DOI":"10.1109\/soccon.2009.5398053","type":"proceedings-article","created":{"date-parts":[[2010,1,26]],"date-time":"2010-01-26T17:38:06Z","timestamp":1264527486000},"page":"223-226","source":"Crossref","is-referenced-by-count":3,"title":["Improved write margin 6T-SRAM for low supply voltage applications"],"prefix":"10.1109","author":[{"given":"Farshad","family":"Moradi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dag T.","family":"Wisland","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamid","family":"Mahmoodi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tuan Vu","family":"Cao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810287"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.883344"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609437"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1393921.1393954"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696326"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859025"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"165","DOI":"10.1109\/ICVD.2005.41","article-title":"Accurate Stacking Effect Macro-modeling of Leakage Power in Sub-100nm Circuits","author":"yang","year":"2005","journal-title":"Proc 18th Int Conf VLSI Design"},{"key":"ref9","article-title":"SRAM cell design for stability methodology","author":"wann","year":"2004","journal-title":"IEEE VLSI-TSA"},{"key":"ref1","first-page":"2778","article-title":"Sub-IV, Robust and Compact 6T SRAM cell in Double Gate MOS technology","author":"thomas","year":"2007","journal-title":"Proc IEEE Int Symp Circ Syst (ISCAS)"}],"event":{"name":"2009 IEEE International SOC Conference (SOCC)","start":{"date-parts":[[2009,9,9]]},"location":"Belfast, Northern Ireland","end":{"date-parts":[[2009,9,11]]}},"container-title":["2009 IEEE International SOC Conference (SOCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5379508\/5397993\/05398053.pdf?arnumber=5398053","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T04:06:33Z","timestamp":1497845193000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5398053\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,9]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/soccon.2009.5398053","relation":{},"subject":[],"published":{"date-parts":[[2009,9]]}}}