{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:06:30Z","timestamp":1740132390834,"version":"3.37.3"},"reference-count":53,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2018,12,1]],"date-time":"2018-12-01T00:00:00Z","timestamp":1543622400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Australian Research Council Linkage","award":["LP140100328"],"award-info":[{"award-number":["LP140100328"]}]},{"name":"Australian Postgraduate Award scholarship","award":["DP150103866"],"award-info":[{"award-number":["DP150103866"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Aerosp. Electron. Syst."],"published-print":{"date-parts":[[2018,12]]},"DOI":"10.1109\/taes.2018.2828201","type":"journal-article","created":{"date-parts":[[2018,4,18]],"date-time":"2018-04-18T20:29:07Z","timestamp":1524083347000},"page":"2695-2712","source":"Crossref","is-referenced-by-count":5,"title":["FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA Designs"],"prefix":"10.1109","volume":"54","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8849-8074","authenticated-orcid":false,"given":"Dimitris","family":"Agiakatsikas","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9313-3034","authenticated-orcid":false,"given":"Ediz","family":"Cetin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oliver","family":"Diessel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1088\/1748-0221\/9\/01\/C01025"},{"article-title":"Developing secure and reliable single device designs with Xilinx 7 series FPGAs or Zynq-7000 AP SoCs using the isolation design flow","year":"2015","author":"hallett","key":"ref38"},{"article-title":"UltraScale devices maximize design integrity with industry-leading SEU resilience and mitigation","year":"2015","author":"derek","key":"ref33"},{"article-title":"Xilinx redefines power, performance, and design productivity with three new 28 nm FPGA families: Virtex-7, Kintex-7, and Artix-7 devices","year":"2012","author":"mehta","key":"ref32"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/REDW.2014.7004595"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/23.659030"},{"journal-title":"Reliability of Computer Systems and Networks Fault Tolerance Analysis and Design","year":"2003","author":"shooman","key":"ref37"},{"journal-title":"Mathemat Programm","year":"2014","author":"maeder","key":"ref36"},{"journal-title":"Performance and Reliability Analysis of Computer Systems An Example-Based Approach Using the SHARPE Software Package","year":"2012","author":"sahner","key":"ref35"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/REDW.2012.6353715"},{"year":"2018","key":"ref28","article-title":"7 Series FPGAs configuration user guide (UG470)"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2016.30"},{"key":"ref29","first-page":"1","article-title":"ESA's SPpace ENVironment information system (SPENVIS): A WWW interface to models of the space environment and its effects","volume":"371","author":"heynderickx","year":"2000","journal-title":"Amer Inst Aeronaut Astronaut"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2671181"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2246581"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2012.2231881"},{"key":"ref22","first-page":"1190","article-title":"Improving Fmax of FPGA circuits employing DPR to recover from configuration memory upsets","author":"cetin","year":"0","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.281"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2015.7231160"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723154"},{"article-title":"Hardware and software fault-tolerance of softcore processors implemented in SRAM-based FPGAs","year":"2012","author":"rollins","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577339"},{"year":"2007","key":"ref50","article-title":"Correcting single-event upsets in Virtex-II platform FPGA configuration memory"},{"year":"2010","key":"ref51","article-title":"Correcting single-event upsets through Virtex partial configuration"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2425653"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/3144533"},{"article-title":"Estimating TMR reliability on FPGAs using Markov models","year":"2008","author":"mcmurtrey","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/5.259424"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554767"},{"year":"2016","key":"ref12","article-title":"Isolation design flow for Xilinx 7 series FPGAs or Zynq-7000 AP SoCs (Vivado Tools)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.82"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2251902"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2012.6408673"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645571"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2011.6132703"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2007.25"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272543"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2015.2492824"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TAES.2016.140914"},{"key":"ref6","volume":"1","author":"kastensmidt","year":"2006","journal-title":"Fault-Tolerance Techniques for SRAM-based FPGAs"},{"year":"2015","key":"ref5","article-title":"TA 8: Science instruments, observatories, and sensor systems"},{"journal-title":"Fault-Tolerant Systems","year":"2010","author":"koren","key":"ref8"},{"key":"ref7","volume":"48","author":"quinn","year":"2015","journal-title":"Improving Fault Tolerance of SRAM-Based FPGAs in Harsh Radiation Environments"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.69"},{"article-title":"Triple module redundancy design techniques for Virtex FPGAs","year":"2006","author":"carmichael","key":"ref9"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2513673"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjjip.17.242"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2562361"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2017.57"},{"article-title":"Configuration scrubbing architectures for high-reliability FPGA systems","year":"2015","author":"stoddard","key":"ref42"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.69"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056798"},{"year":"2017","key":"ref43","article-title":"Soft error mitigation controller product guide (PG036)"}],"container-title":["IEEE Transactions on Aerospace and Electronic Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7\/8563118\/08340787.pdf?arnumber=8340787","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T04:39:56Z","timestamp":1643258396000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8340787\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12]]},"references-count":53,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/taes.2018.2828201","relation":{},"ISSN":["0018-9251","1557-9603","2371-9877"],"issn-type":[{"type":"print","value":"0018-9251"},{"type":"electronic","value":"1557-9603"},{"type":"electronic","value":"2371-9877"}],"subject":[],"published":{"date-parts":[[2018,12]]}}}