{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,7]],"date-time":"2026-05-07T15:44:34Z","timestamp":1778168674931,"version":"3.51.4"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[1977,3,1]],"date-time":"1977-03-01T00:00:00Z","timestamp":226022400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[1977,3,1]],"date-time":"1977-03-01T00:00:00Z","timestamp":226022400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[1977,3,1]],"date-time":"1977-03-01T00:00:00Z","timestamp":226022400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[1977,3]]},"DOI":"10.1109\/tc.1977.1674821","type":"journal-article","created":{"date-parts":[[2007,9,4]],"date-time":"2007-09-04T16:35:10Z","timestamp":1188923710000},"page":"281-288","source":"Crossref","is-referenced-by-count":54,"title":["Design of Ternary COS\/MOS Memory and Sequential Circuits"],"prefix":"10.1109","volume":"C-26","author":[{"family":"Mouftah","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, University of Toronto"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Jordan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1972.223544"},{"key":"ref11","first-page":"89","article-title":"an approach to multivalued sequential logic","author":"irving","year":"1973","journal-title":"Conf Rec 1973 Int Symp on Multiple-Valued Logic"},{"key":"ref12","first-page":"209","article-title":"on multiple-valued memory elements","author":"shiva","year":"1974","journal-title":"Proc 1974 Int Symp on Multiple-Valued Logic"},{"key":"ref13","first-page":"627","article-title":"switching response of complementary symmetry mos transistor logic circuits","volume":"xxv","author":"burns","year":"1964","journal-title":"RCA Rev"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1971.8333"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1973.1050440"},{"key":"ref16","first-page":"59","article-title":"electronic implementation of multi-valued logic networks","author":"vranesic","year":"1974","journal-title":"Proc 1974 Int Symp on Multiple-Valued Logic"},{"key":"ref17","first-page":"80","article-title":"trilogic, a three-level logic system provides greater memory density","author":"kaniel","year":"1973","journal-title":"EDN"},{"key":"ref18","year":"0","journal-title":"COS\/MOS Integrated Circuits Manual"},{"key":"ref19","year":"1974","journal-title":"COS\/MOS Digital Integrated Circuits Selection Guide Data Application Notes RCA Solid State Databook Series"},{"key":"ref4","first-page":"88","article-title":"tunnel-diode circuits for ternary logic","author":"hasegawa","year":"1964","journal-title":"Elec Commun Japan"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1049\/pi-c.1962.0028"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1049\/el:19740350"},{"key":"ref5","first-page":"285","article-title":"integrated circuits for ternary logic","author":"mouftah","year":"1974","journal-title":"Proc 1974 Int Symp on Multiple-Valued Logic"},{"key":"ref8","author":"mouftah","year":"1975","journal-title":"Three-valued logic and its implementation with COS\/MOS integrated circuits"},{"key":"ref7","first-page":"359","article-title":"a design technique for an integrable ternary arithmetic unit","author":"mouftah","year":"1975","journal-title":"Proc 1975 Int Symp Multiple-Valued Logic"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1049\/piee.1968.0246"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1965.264050"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1049\/piee.1969.0177"},{"key":"ref20","first-page":"1337","article-title":"ternary read-only-memory","volume":"14","author":"maley","year":"1971","journal-title":"IBM Tech Disclosure Bull"},{"key":"ref21","first-page":"2384","article-title":"ternary latches","volume":"14","author":"maley","year":"1972","journal-title":"IBM Tech Disclosure Bull"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/35155\/01674821.pdf?arnumber=1674821","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,9]],"date-time":"2025-07-09T23:08:23Z","timestamp":1752102503000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1674821\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1977,3]]},"references-count":21,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tc.1977.1674821","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[1977,3]]}}}