{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T14:17:21Z","timestamp":1775053041326,"version":"3.50.1"},"reference-count":16,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[1978,6,1]],"date-time":"1978-06-01T00:00:00Z","timestamp":265507200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[1978,6,1]],"date-time":"1978-06-01T00:00:00Z","timestamp":265507200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[1978,6,1]],"date-time":"1978-06-01T00:00:00Z","timestamp":265507200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[1978,6]]},"DOI":"10.1109\/tc.1978.1675139","type":"journal-article","created":{"date-parts":[[2007,9,4]],"date-time":"2007-09-04T16:35:10Z","timestamp":1188923710000},"page":"491-499","source":"Crossref","is-referenced-by-count":200,"title":["Strongly Fault Secure Logic Networks"],"prefix":"10.1109","volume":"C-27","author":[{"family":"Smith","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Wisconsin-Madison"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Metze","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675338"},{"key":"ref11","first-page":"124","article-title":"design of totally self-checking asynchronous and synchronous sequential machines","author":"ozguner","year":"1977","journal-title":"Proc 7th Annu Int Conf on Fault-Tolerant Computing"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223620"},{"key":"ref13","first-page":"18","article-title":"checked binary addition with checksum codes","volume":"1","author":"wakerly","year":"1976","journal-title":"J Design Automation and Fault Tolerant Computing"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0402"},{"key":"ref15","author":"allen","year":"1966","journal-title":"Design of digital memories that tolerant all classes of defects"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.224020"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"658","DOI":"10.1109\/T-C.1974.224014","article-title":"partially self-checking circuits and their use in performing logical operations","volume":"c 23","author":"wakerly","year":"1974","journal-title":"IEEE Transactions on Computers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1978.1675011"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"1286","DOI":"10.1109\/T-C.1971.223129","article-title":"fault equivalence in combinational logic networks","volume":"c 20","author":"mccluskey","year":"1971","journal-title":"IEEE Transactions on Computers"},{"key":"ref5","author":"smith","year":"1976","journal-title":"The design of totally self-checking combinational circuits"},{"key":"ref8","first-page":"321","article-title":"the design of totally self-checking check circuits for a class of unordered codes","volume":"1","author":"smith","year":"1977","journal-title":"J Design Automation and Fault-Tolerant Comput"},{"key":"ref7","first-page":"205","author":"tryon","year":"1962","journal-title":"Redundancy Techniques for Computing Systems"},{"key":"ref2","author":"anderson","year":"1971","journal-title":"Design of self-checking digital networks using coding techniques"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1966.264376"},{"key":"ref1","first-page":"878","article-title":"design of dynamically checked computers","volume":"2","author":"carter","year":"1968","journal-title":"IFIP 68"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/35170\/01675139.pdf?arnumber=1675139","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,9]],"date-time":"2025-07-09T23:08:33Z","timestamp":1752102513000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1675139\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1978,6]]},"references-count":16,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tc.1978.1675139","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[1978,6]]}}}