{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,11]],"date-time":"2025-07-11T00:01:05Z","timestamp":1752192065584,"version":"3.41.2"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[1979,11,1]],"date-time":"1979-11-01T00:00:00Z","timestamp":310262400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[1979,11,1]],"date-time":"1979-11-01T00:00:00Z","timestamp":310262400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[1979,11,1]],"date-time":"1979-11-01T00:00:00Z","timestamp":310262400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[1979,11]]},"DOI":"10.1109\/tc.1979.1675261","type":"journal-article","created":{"date-parts":[[2007,9,4]],"date-time":"2007-09-04T16:35:10Z","timestamp":1188923710000},"page":"811-818","source":"Crossref","is-referenced-by-count":3,"title":["Universal Multicode STT State Assignments for Asynchronous Sequential Machines"],"prefix":"10.1109","volume":"C-28","author":[{"family":"Nanya","sequence":"first","affiliation":[{"name":"Central Research Laboratories, Nippon Electric Company, Ltd."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Tohma","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"universal state assignment for asynchronous sequential circuits","author":"mago","year":"1969","journal-title":"IEEE Computer Group Repository"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1966.264362"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1978.1674972"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1976.1674720"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1978.1675192"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SWAT.1970.2"},{"journal-title":"Asynchronous Sequential Switching Circuits","year":"1969","author":"unger","key":"ref8"},{"journal-title":"State reduction and state assignments for asynchronous sequential machines","year":"1967","author":"frieds","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/321160.321169"},{"journal-title":"Error Correcting Codes","year":"1972","author":"peterson","key":"ref9"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"541","DOI":"10.1109\/T-C.1969.222707","article-title":"universal single transition time asynchronous state assignments","volume":"c 18","author":"friedman","year":"1969","journal-title":"IEEE Transactions on Computers"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/35176\/01675261.pdf?arnumber=1675261","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,9]],"date-time":"2025-07-09T23:08:46Z","timestamp":1752102526000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1675261\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1979,11]]},"references-count":11,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tc.1979.1675261","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"type":"print","value":"0018-9340"},{"type":"electronic","value":"1557-9956"},{"type":"electronic","value":"2326-3814"}],"subject":[],"published":{"date-parts":[[1979,11]]}}}