{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,2]],"date-time":"2025-08-02T14:44:44Z","timestamp":1754145884622,"version":"3.41.2"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[1981,11,1]],"date-time":"1981-11-01T00:00:00Z","timestamp":373420800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[1981,11,1]],"date-time":"1981-11-01T00:00:00Z","timestamp":373420800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[1981,11,1]],"date-time":"1981-11-01T00:00:00Z","timestamp":373420800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[1981,11]]},"DOI":"10.1109\/tc.1981.1675718","type":"journal-article","created":{"date-parts":[[2007,9,4]],"date-time":"2007-09-04T16:35:10Z","timestamp":1188923710000},"page":"875-884","source":"Crossref","is-referenced-by-count":18,"title":["Design of Testable Structures Defined by Simple Loops"],"prefix":"10.1109","volume":"C-30","author":[{"family":"Abraham","sequence":"first","affiliation":[{"name":"Coordinated Science Laboratory, University of Illinois"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Gajski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Computer Organization and Microprogramming","year":"1972","author":"chu","key":"ref4"},{"key":"ref3","first-page":"413","author":"carter","year":"1974","journal-title":"Computer System Reliability"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FOCS.1967.33"},{"journal-title":"Logic Design of Digital Systems","year":"1978","author":"dietmeyer","key":"ref6"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223205"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1976.1674660"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1979.1600118"},{"journal-title":"High Speed Computer and Algorithm Organization","year":"1977","author":"gajski","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-95424-5"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/382168.382170"},{"key":"ref1","article-title":"an algorithm for efficient layouts of parallel suffix solutions","author":"bilgory","year":"1981","journal-title":"Proc Int Conf on Parallel Processing"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/35199\/01675718.pdf?arnumber=1675718","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,17]],"date-time":"2025-07-17T17:56:33Z","timestamp":1752774993000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1675718\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1981,11]]},"references-count":11,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tc.1981.1675718","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"type":"print","value":"0018-9340"},{"type":"electronic","value":"1557-9956"},{"type":"electronic","value":"2326-3814"}],"subject":[],"published":{"date-parts":[[1981,11]]}}}