{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,2]],"date-time":"2025-08-02T14:44:49Z","timestamp":1754145889001,"version":"3.41.2"},"reference-count":9,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[1981,8,1]],"date-time":"1981-08-01T00:00:00Z","timestamp":365472000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[1981,8,1]],"date-time":"1981-08-01T00:00:00Z","timestamp":365472000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[1981,8,1]],"date-time":"1981-08-01T00:00:00Z","timestamp":365472000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[1981,8]]},"DOI":"10.1109\/tc.1981.1675842","type":"journal-article","created":{"date-parts":[[2007,9,4]],"date-time":"2007-09-04T16:35:10Z","timestamp":1188923710000},"page":"572-581","source":"Crossref","is-referenced-by-count":9,"title":["A Layout System for the Random Logic Portion of an MOS LSI Chip"],"prefix":"10.1109","volume":"C-30","author":[{"family":"Shirakawa","sequence":"first","affiliation":[{"name":"Departrment of Electronic Engineering, Osaka University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Okuda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Harada","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Tani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Ozaki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1979.1084695"},{"key":"ref3","first-page":"384","article-title":"a heuristic procedure for ordering mos array","author":"yoshizawa","year":"1975","journal-title":"Proc 12th Des Automat Workshop"},{"journal-title":"The Design and Analysis of Computer Algorithms","year":"1974","author":"aho","key":"ref6"},{"journal-title":"Logic Design and Switching Theory","year":"1979","author":"muroga","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/800158.805069"},{"key":"ref7","first-page":"657","article-title":"np-completeness of the problem of finding a minimum-clique-number interval graph containing a given graph as a subgraph","author":"kashiwabara","year":"1979","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223285"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1981.1585451"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1967.1049816"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/35206\/01675842.pdf?arnumber=1675842","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,17]],"date-time":"2025-07-17T17:56:43Z","timestamp":1752775003000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1675842\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1981,8]]},"references-count":9,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tc.1981.1675842","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"type":"print","value":"0018-9340"},{"type":"electronic","value":"1557-9956"},{"type":"electronic","value":"2326-3814"}],"subject":[],"published":{"date-parts":[[1981,8]]}}}