{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,6]],"date-time":"2025-12-06T16:56:05Z","timestamp":1765040165449,"version":"3.41.2"},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[1982,9,1]],"date-time":"1982-09-01T00:00:00Z","timestamp":399686400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[1982,9,1]],"date-time":"1982-09-01T00:00:00Z","timestamp":399686400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[1982,9,1]],"date-time":"1982-09-01T00:00:00Z","timestamp":399686400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[1982,9]]},"DOI":"10.1109\/tc.1982.1676102","type":"journal-article","created":{"date-parts":[[2007,9,4]],"date-time":"2007-09-04T16:35:10Z","timestamp":1188923710000},"page":"870-882","source":"Crossref","is-referenced-by-count":6,"title":["Logic Networks of Carry&amp;#8211;Save Adders"],"prefix":"10.1109","volume":"C-31","author":[{"family":"Hung Chi Lai","sequence":"first","affiliation":[{"name":"Microtechnology Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Muroga","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1967.264617"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JRPROC.1961.287779"},{"journal-title":"VLSI System Design","year":"1982","author":"muroga","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.223778"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1967.264812"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1964.263830"},{"journal-title":"A study of current logic design problems","year":"1976","author":"lai","key":"ref7"},{"key":"ref2","first-page":"74","article-title":"cascade adder improves system speed for high-speed multiply operations","volume":"18","author":"partridge","year":"1973","journal-title":"EDN"},{"journal-title":"Logic Design and Switching Theory","year":"1979","author":"muroga","key":"ref9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675433"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/35219\/01676102.pdf?arnumber=1676102","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,18]],"date-time":"2025-07-18T17:44:22Z","timestamp":1752860662000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1676102\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1982,9]]},"references-count":10,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tc.1982.1676102","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"type":"print","value":"0018-9340"},{"type":"electronic","value":"1557-9956"},{"type":"electronic","value":"2326-3814"}],"subject":[],"published":{"date-parts":[[1982,9]]}}}