{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,22]],"date-time":"2025-10-22T17:44:23Z","timestamp":1761155063312},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[1985,11,1]],"date-time":"1985-11-01T00:00:00Z","timestamp":499651200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[1985,11]]},"DOI":"10.1109\/tc.1985.1676536","type":"journal-article","created":{"date-parts":[[2007,9,4]],"date-time":"2007-09-04T20:35:10Z","timestamp":1188938110000},"page":"1033-1044","source":"Crossref","is-referenced-by-count":65,"title":["Gracefully Degradable Processor Arrays"],"prefix":"10.1109","volume":"C-34","author":[{"family":"Fortes","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Raghavendra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref32","author":"fortes","year":"1984","journal-title":"Gracefully degradable array processors"},{"key":"ref31","author":"pradhan","year":"0","journal-title":"Fault-Tolerant Computing Theory and Techniques"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(85)90029-2"},{"key":"ref10","author":"moldovan","year":"0","journal-title":"Partitioning of algorithms for execution in fixed size VLSI architectures"},{"key":"ref11","year":"1983"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1976.1674712"},{"key":"ref13","first-page":"123","article-title":"reliability aspects of the illiac iv computer","author":"baqai","year":"0","journal-title":"Proc 1976 Int Conf Parallel Processing"},{"key":"ref14","first-page":"436","article-title":"fault-tolerant architectures for multiprocessors and vlsi systems","author":"pradhan","year":"1983","journal-title":"Proc 12th Symp Fault-Tolerant Computing"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1983.1676134"},{"key":"ref16","author":"koren","year":"1982","journal-title":"On area and yield considerations for fault tolerant VLSI processor arrays"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1676058"},{"key":"ref18","first-page":"744","article-title":"on the vlsi implementation of fault-tolerant architectures","author":"raghavendra","year":"0","journal-title":"Proc 1983 Int Conf Comput Des VLSI Comput"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1067649.801727"},{"key":"ref28","author":"kuhn","year":"1980","journal-title":"Optimization and interconnection complexity for parallel processors sijngle stage networks and decision trees"},{"key":"ref4","author":"kung","year":"1980","journal-title":"Introduction to VLSI Systems"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(84)90010-8"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675684"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1982.1653826"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1675922"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1675929"},{"key":"ref8","first-page":"29","article-title":"numerical experiments with the massively parallel processor","author":"gallopoulos","year":"0","journal-title":"Proc 1983 Int Conf Parallel Processing"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/360827.360844"},{"key":"ref2","author":"uhr","year":"1982","journal-title":"Computer Arrays and Networks Algorithm-Structured Parallel Architectures"},{"key":"ref9","author":"fortes","year":"1983","journal-title":"Algorithm transformations for parallel processing and VLSI architecture design"},{"key":"ref1","author":"hwang","year":"1984","journal-title":"Parallel Computer Architecture"},{"key":"ref20","article-title":"area and delay penalties in restructurable wafer scale arrays","author":"greene","year":"1982","journal-title":"Proc 3rd Caltech Conf VLSI"},{"key":"ref22","first-page":"330","article-title":"low cost schemes for fault tolerance in matrix operations with processor arrays","author":"kuang","year":"0","journal-title":"Proc 1st Symp Comput Architecture"},{"key":"ref21","first-page":"76","article-title":"serial convolver to be fault-tolerant","author":"smith","year":"1983","journal-title":"Electron"},{"key":"ref24","article-title":"dynamically reconfigurable fault-tolerant array processors","author":"fortes","year":"1984","journal-title":"Proc 14th Fault-Tolerant Comput Symp"},{"key":"ref23","first-page":"145","article-title":"yield enhancement by fault-tolerant systolic array (summary)","author":"kuhn","year":"1982","journal-title":"USC Workshop VLSI Modern Signal Processing"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1978.1675145"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675654"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/35242\/01676536.pdf?arnumber=1676536","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:40:13Z","timestamp":1638218413000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1676536\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1985,11]]},"references-count":32,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tc.1985.1676536","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[1985,11]]}}}