{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T15:28:01Z","timestamp":1774798081629,"version":"3.50.1"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[1987,2,1]],"date-time":"1987-02-01T00:00:00Z","timestamp":539136000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[1987,2,1]],"date-time":"1987-02-01T00:00:00Z","timestamp":539136000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[1987,2,1]],"date-time":"1987-02-01T00:00:00Z","timestamp":539136000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[1987,2]]},"DOI":"10.1109\/tc.1987.1676878","type":"journal-article","created":{"date-parts":[[2007,9,4]],"date-time":"2007-09-04T16:35:10Z","timestamp":1188923710000},"page":"157-166","source":"Crossref","is-referenced-by-count":9,"title":["Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables"],"prefix":"10.1109","volume":"C-36","author":[{"family":"Hung Chi Lai","sequence":"first","affiliation":[{"name":"Fujitsu Microelectronics, Inc."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Muroga","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1985.5009404"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/BF01108520"},{"key":"ref11","author":"ikeno","year":"1968","journal-title":"Electrical Commun Lab Tech J"},{"key":"ref12","author":"lai","year":"1976","journal-title":"A study of current logic design problems"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675433"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/BF00977257"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.223778"},{"key":"ref16","author":"liu","year":"1968","journal-title":"A code for zero-one integer linear programming by implicit enumeration"},{"key":"ref17","year":"1970","journal-title":"Manual of Logic Circuits"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-8243-4_5"},{"key":"ref19","author":"muroga","year":"1971","journal-title":"Threshold Logic and Its Applications"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1983.1676144"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5008920"},{"key":"ref27","author":"nakagawa","year":"1984","journal-title":"Design algorithm of optimal NOR networks by the branch-and?linois Urbana Rep bound approach"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1287\/opre.19.4.1090"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675229"},{"key":"ref29","author":"young","year":"1977","journal-title":"A code for zero-one integer programming ILLIP-2 (A programming manual for ILLIP-2)"},{"key":"ref5","author":"cheng","year":"1982","journal-title":"Minimal parallel binary adders with AND\/OR gates and a scheme for a compact parallel multiplier"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1963.263531"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1969.222593"},{"key":"ref2","author":"baugh","year":"1969","journal-title":"Optimum network design using NOR and NOR-AND gates by integer programming"},{"key":"ref9","author":"hohulin","year":"0","journal-title":"A code for solving network synthesis problems by implicit enumeration using the all-interconnection inequality formulation"},{"key":"ref1","author":"alkhateeb","year":"1981","journal-title":"A study of NOR\/NAND networks"},{"key":"ref20","author":"muroga","year":"1982","journal-title":"VLSI System Design"},{"key":"ref22","author":"muroga","year":"1968","journal-title":"Logical design of an optimum network by integer linear programming?Part II"},{"key":"ref21","author":"muroga","year":"1968","journal-title":"Logical design of an optimum network by integer linear programming?Part I"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1976.1674714"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5009010"},{"key":"ref26","author":"nakagawa","year":"1971","journal-title":"Pruning and branching methods for designing optimal networks by the branch-and-bound method"},{"key":"ref25","author":"nakagawa","year":"1985","journal-title":"Reference manual of FORTRAN program ILLOD-(NOR-B) for optimal NOR networks-Revised"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/35261\/01676878.pdf?arnumber=1676878","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,22]],"date-time":"2025-07-22T18:02:40Z","timestamp":1753207360000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1676878\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1987,2]]},"references-count":30,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tc.1987.1676878","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"value":"0018-9340","type":"print"},{"value":"1557-9956","type":"electronic"},{"value":"2326-3814","type":"electronic"}],"subject":[],"published":{"date-parts":[[1987,2]]}}}