{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,15]],"date-time":"2026-01-15T22:33:37Z","timestamp":1768516417088,"version":"3.49.0"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2003,1]]},"DOI":"10.1109\/tc.2003.1159750","type":"journal-article","created":{"date-parts":[[2003,3,7]],"date-time":"2003-03-07T18:58:16Z","timestamp":1047063496000},"page":"4-20","source":"Crossref","is-referenced-by-count":31,"title":["Minimum register instruction sequencing to reduce register spills in out-of-order issue superscalar architectures"],"prefix":"10.1109","volume":"52","author":[{"given":"R.","family":"Govindarajan","sequence":"first","affiliation":[]},{"family":"Hongbo Yang","sequence":"additional","affiliation":[]},{"given":"J.N.","family":"Amaral","sequence":"additional","affiliation":[]},{"family":"Chihong Zhang","sequence":"additional","affiliation":[]},{"given":"G.R.","family":"Gao","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref1","volume-title":"CompilersPrinciples, Techniques, and Tools","author":"Aho","year":"1988"},{"key":"ref2","article-title":"Optimal Software Pipelining with Function Unit and Register Constraints","volume-title":"McGill Univ., Montr\u00e9al, Qu\u00e9bec","author":"Altman","year":"1995"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/378795.378854"},{"key":"ref4","article-title":"URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures","volume-title":"Proc. Conf. Parallel Architectures and Compilation Techniques (PACT \u201998)","author":"Berson"},{"key":"ref5","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-48319-5_16","article-title":"Integrated Instruction Scheduling and Register Allocation Techniques","volume-title":"Proc. 11th Int\u2019l Workshop Languages and Compilers for Parallel Computing","author":"Berson"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/106972.106986"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/143095.143143"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/177492.177575"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/321958.321971"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/800230.806984"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/0096-0551(81)90048-5"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/88616.88621"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291010"},{"key":"ref14","volume-title":"Advanced Topics in Dataflow Computing and Multithreading","author":"Gao","year":"1995"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/237721.237777"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/12276.13312"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/55364.55407"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1002\/(SICI)1097-024X(199608)26:8<929::AID-SPE40>3.0.CO;2-T"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44905-1_5"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2001.924962"},{"issue":"3","key":"ref21","first-page":"155","article-title":"A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs","volume":"1","author":"Hendren","year":"1993","journal-title":"The J. Programming Languages"},{"key":"ref22","first-page":"270","volume-title":"Integer Programming and Network Flows","author":"Hu","year":"1969"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/BF01205185"},{"key":"ref24","year":"2000","journal-title":"Intel IA-64 Architecture Software Developer\u2019s Manual"},{"key":"ref25","first-page":"228","article-title":"Scheduling Expression DAGs for Minimal Register Need","volume-title":"Proc. Eighth Int\u2019l Symp. Programming Languages: on Programming Languages: Implementations, Logics, and Programs (PLILP \u201996)","author":"Kessler"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1998.727189"},{"key":"ref27","article-title":"Combining Register Allocation and Instruction Scheduling","author":"Motwani","year":"1996"},{"key":"ref28","volume-title":"Advanced Compiler Design and Implementation","author":"Muchnick","year":"1997"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476819"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/178243.178427"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/155090.155114"},{"key":"ref32","article-title":"Linear Scan Register Allocation","author":"Poletto","year":"1998","journal-title":"ACM Trans. Programming Languages and Systems"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/113445.113467"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1137\/0204020"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/321607.321620"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1997.644005"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/5.476078"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45306-7_15"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/277650.277714"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1999.807420"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1147\/rd.341.0085"},{"key":"ref42","volume-title":"The Design of an Optimizing Compiler","author":"Wulf","year":"1975"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/25989\/01159750.pdf?arnumber=1159750","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,16]],"date-time":"2025-03-16T04:59:30Z","timestamp":1742101170000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1159750\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,1]]},"references-count":42,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2003,1]]}},"URL":"https:\/\/doi.org\/10.1109\/tc.2003.1159750","relation":{},"ISSN":["0018-9340"],"issn-type":[{"value":"0018-9340","type":"print"}],"subject":[],"published":{"date-parts":[[2003,1]]}}}